Abstract: A method for processing one or more bursts including receiving at least a portion of a first burst comprising one or more protocol data units. The method includes receiving a sequence number for the first burst. The method includes writing the sequence number and the first burst to a physical-layer queue, such that the first burst is concatenated to the sequence number in the physical-layer queue. The sequence number may identify the first burst from one or more second bursts written to the physical-layer queue preceding or following the first burst.

Abstract: An apparatus for receiving one or more protocol data units (PDUs) from a word aligned queue including a media access control (MAC) physical-layer (PHY) coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor. The MPC is configured to access a reception physical-layer queue storing a burst, such that the reception physical-layer queue includes a plurality of word lines. The burst includes one or more PDUs that each occupy one or more word lines of the reception physical-layer queue, such that a particular word line stores a portion of a first PDU and a portion of second PDU. The MPC is also configured to receive from the reception physical-layer queue the first PDU including the portion of the first PDU stored in the selected word line.

Abstract: An apparatus for receiving one or more protocol data units (PDUs) from a word aligned queue including a media access control (MAC) physical-layer (PHY) coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor. The MPC is configured to access a reception physical-layer queue storing a burst, such that the reception physical-layer queue includes a plurality of word lines. The burst includes one or more PDUs that each occupy one or more word lines of the reception physical-layer queue, such that a particular word line stores a portion of a first PDU and a portion of second PDU. The MPC is also configured to receive from the reception physical-layer queue the first PDU including the portion of the first PDU stored in the selected word line.

Abstract: An apparatus for receiving one or more protocol data units (PDUs) from a word aligned queue including a media access control (MAC) physical-layer (PHY) coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor. The MPC is configured to access a reception physical-layer queue storing a burst, such that the reception physical-layer queue includes a plurality of word lines. The burst includes one or more PDUs that each occupy one or more word lines of the reception physical-layer queue, such that a particular word line stores a portion of a first PDU and a portion of second PDU. The MPC is also configured to receive from the reception physical-layer queue the first PDU including the portion of the first PDU stored in the selected word line.

Abstract: A system for verifying a cipher-based message authentication code (CMAC), including a reception (RX) module logically residing between a physical layer controller (PHY) and a media access controller (MAC) processor, such that the RX module is configured to receive one or more portions of the CMAC with one or more bursts, process the one or more bursts, and write the one or more portions of the CMAC to one or more memory locations in a memory. The system also includes a transmission (TX) module logically residing between the PHY and the MAC processor, such that the TX module configured to verify the CMAC concurrently as the RX module processes the one or more bursts.

Abstract: Disclosed are processors for implementing the Media-access control layer of a network device.

Abstract: A messaging system includes a first mailbox storage assigned to receive a message for the first processor and a first lock indicator having a first state to indicate that the first mailbox storage can receive a message and a second state to indicate that the first mailbox storage cannot receive a message. The system also includes a second mailbox storage assigned to receive a message for the second processor and a second lock indicator having a first state to indicate that the second mailbox storage can receive a message and a second state to indicate that the second mailbox storage cannot receive a message. The lock indicators are changed to their second state when a message is placed in their respective mailbox storage and are changes to their first state in response to its contents being read by the respective processor.

Abstract: A method for operating a media-access control unit in communications network includes placing the unit in a scan mode where the cyclic-prefix length and frame length of frames of data transmitted by a base station are ascertained and one or more parameters relating to the signal quality of the base station are collected. Data is not exchanged with a higher protocol-layer unit during this scan mode. The method also includes the unit remaining in the scan mode until at least a point in time when the unit is receiving frame control headers at an interval equal to the ascertained frame length. The unit is thereafter placed in a run mode in which the unit processes at least one flow of data to the higher protocol-layer unit once the cyclic-prefix length and the frame length are ascertained.

Abstract: A processor is provided that includes inputs to receive headers and payloads of messages in block form, a cipher key, a counter block, and an indication that a data block is ready to be received at the processor's first input, and that outputs a data block processes according to a CCM protocol and a signal requesting the provision of a data block at the processor input. The processor also includes first and second cipher circuits generating ciphered results that are a function of a input data block and an input cipher key. Furthermore, the processor includes a controller that processes a first sequence of data blocks through the first cipher circuit to generate a message integrity code and a second sequence of data blocks through the second cipher circuit to generate a set of ciphered data blocks.

Abstract: An apparatus includes a physical layer controller (PHY) and a media access control coprocessor (MPC). The PHY includes a plurality of physical-layer queues, wherein each of the plurality of physical-layer queues is associated with one of a plurality of bursts, wherein each of the plurality of bursts includes one or more protocol data units (PDUs). The MPC is configured to receive a first PDU associated with a first burst of the plurality of bursts and write the first PDU of the first burst to a first physical-layer queue of the plurality of physical-layer queues. The MPC is further configured to receive a second PDU and determine that the second PDU is associated with a second burst of the plurality of bursts. The MPC also being configured to write the second PDU to a second physical-layer queue, wherein the second physical-layer queue is associated with the second burst.

Abstract: A system for verifying a cipher-based message authentication code (CMAC), including a reception (RX) module logically residing between a physical layer controller (PHY) and a media access controller (MAC) processor, such that the RX module is configured to receive one or more portions of the CMAC with one or more bursts, process the one or more bursts, and write the one or more portions of the CMAC to one or more memory locations in a memory. The system also includes a transmission (TX) module logically residing between the PHY and the MAC processor, such that the TX module configured to verify the CMAC concurrently as the RX module processes the one ore more bursts.

Abstract: An apparatus for processing a protocol data unit (PDU) includes a transmit (TX) module, a physical layer controller (PHY), and a reception (RX) module. The TX module is configured to receive a transmit descriptor that comprises a plurality of fields, wherein the fields contain information for preparing a first PDU. The PHY is configured to receive at least a portion of a second PDU into a reception (RX) physical-layer queue, the second PDU having a header. The RX module is configured to receive a receive descriptor, wherein the receive descriptor includes a plurality of fields having information for processing the second PDU. The RX module is further configured to process the second PDU according to the receive descriptor in parallel with the TX module processing the first PDU based on the transmit descriptor.

Abstract: A MAC unit processes the flow of data a first processor and a physical-layer control unit of a network component. The first processor processes the data flow between a higher protocol-layer unit and the MAC and assigns connection identifiers to each outgoing MAC protocol-data unit. The MAC unit includes a connection port adapted to couple to the first processor and a second processor that receives outgoing MAC protocol-data units generated by the first processor and generates outgoing FEC blocks therefrom for outputting to the input port of the physical-layer control unit. The second processor having an output port to provide outgoing FEC blocks to the physical-layer control unit and an input port to receive incoming FEC blocks from the physical-layer control unit. The second processor is adapted to generate incoming MAC protocol-data units from incoming FEC blocks received at its input port and to output them on the connection port.

Abstract: A MAC unit is provided that processes the flow of data between a higher protocol-layer unit and a physical-layer control unit of a network communications component. The MAC unit includes a first processor that receives high-level data units from the higher protocol-layer unit and generates outgoing MAC protocol-data units therefrom. The MAC unit also includes a second processor that receives outgoing MAC protocol-data units generated by the first processor and generates outgoing FEC blocks therefrom for outputting to the input port of the physical-layer control unit. In addition the MAC unit includes a MAC-PDU reception buffer accessible by the first and second processors, the second processor storing incoming MAC protocol-data units in the MAC-PDU reception buffer, and the first processor reading incoming MAC protocol-data units from the MAC-PDU reception buffer.

Abstract: A method for transmitting a protocol data unit (PDU) includes receiving one or more Ethernet packets and reading a header associated with each of the one or more Ethernet packets. The method further includes generating a transmit descriptor that includes a plurality of fields containing information for preparing a protocol data unit (PDU), and preparing a PDU according to the transmit descriptor. The method also includes transmitting a burst, wherein the burst includes one or more PDUs.

Abstract: An apparatus for receiving one or more protocol data units (PDUs) from a word aligned queue including a media access control (MAC) physical-layer (PHY) coprocessor (MPC) logically residing between a physical-layer controller and a media access controller (MAC) processor. The MPC is configured to access a reception physical-layer queue storing a burst, such that the reception physical-layer queue includes a plurality of word lines. The burst includes one or more PDUs that each occupy one or more word lines of the reception physical-layer queue, such that a particular word line stores a portion of a first PDU and a portion of second PDU. The MPC is also configured to receive from the reception physical-layer queue the first PDU including the portion of the first PDU stored in the selected word line.

Abstract: A method for processing one or more bursts including receiving at least a portion of a first burst comprising one or more protocol data units. The method includes receiving a sequence number for the first burst. The method includes writing the sequence number and the first burst to a physical-layer queue, such that the first burst is concatenated to the sequence number in the physical-layer queue. The sequence number may identify the first burst from one or more second bursts written to the physical-layer queue preceding or following the first burst.

Abstract: Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device. In one aspect, interface buses group the data lines according to groups of bits, and include group-enable lines to convey a representation of which groups of data lines are active for each data transfer operation. In another aspect, exemplary interface buses include burst-length lines to convey a representation of the number of data bursts in a burst sequence, thereby obviating the need to provide sequential addresses over the bus. Exemplary bus bridges are capable of interpreting the signals on the interface bus and transferring data bursts between the interface bus and one or more memory units within the device.

Abstract: Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device. In one aspect, interface buses group the data lines according to groups of bits, and include group-enable lines to convey a representation of which groups of data lines are active for each data transfer operation. In another aspect, exemplary interface buses include burst-length lines to convey a representation of the number of data bursts in a burst sequence, thereby obviating the need to provide sequential addresses over the bus. Exemplary bus bridges are capable of interpreting the signals on the interface bus and transferring data bursts between the interface bus and one or more memory units within the device.

Abstract: Disclosed are apparatuses and methods to process message data according to a cipher block chaining messaging authentication code (CCM) protocol