Abstract: It is described a transmitter device (100) and a method for transmitting an analog signal (251, 261) via an electric cable (192).

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: In some aspects, the disclosure is directed to methods and systems for a device including a physical interface with electrical connection to a communication channel, and circuitry configured to detect energy received at the physical interface, wait a predetermined length of a time until the beginning of a time slot, monitor the physical interface during the time slot for a predefined pattern from the communication channel, and upon detection of the predefined pattern, transition the device to an increased-power mode.

Abstract: A transceiver system includes a transmitter circuit having a line driver with a programmable signal level to generate a transmit signal for transmission in an automotive environment over an unshielded-twisted pair (UTP) cable. The transceiver system further includes a physical layer (PHY) receiver. The PHY receiver includes a high-pass filter (HPF), an adaptive feed-forward equalizer (FFE) block and a noise aware adaptation block. The HPF rejects transient noise of a received signal, and the FFE block receives a digital signal and adaptively filters out narrowband continuous wave (CW) noise using an adaptation signal. The digital signal is based on the received signal, and the noise aware adaptation block receives an error signal and generates the adaptation signal. The error signal is generated based on an equalized signal of the FFE block and an estimated signal. The combined transmit and receive circuitry allow lowering emission while rejecting strong receiver automotive noises.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A transceiver system includes a transmitter circuit having a line driver with a programmable signal level to generate a transmit signal for transmission in an automotive environment over an unshielded-twisted pair (UTP) cable. The transceiver system further includes a physical layer (PHY) receiver. The PHY receiver includes a high-pass filter (HPF), an adaptive feed-forward equalizer (FFE) block and a noise aware adaptation block. The HPF rejects transient noise of a received signal, and the FFE block receives a digital signal and adaptively filters out narrowband continuous wave (CW) noise using an adaptation signal. The digital signal is based on the received signal, and the noise aware adaptation block receives an error signal and generates the adaptation signal. The error signal is generated based on an equalized signal of the FFE block and an estimated signal. The combined transmit and receive circuitry allow lowering emission while rejecting strong receiver automotive noises.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: In some aspects, the disclosure is directed to methods and systems for a device including a physical interface with electrical connection to a communication channel, and circuitry configured to detect energy received at the physical interface, wait a predetermined length of a time until the beginning of a time slot, monitor the physical interface during the time slot for a predefined pattern from the communication channel, and upon detection of the predefined pattern, transition the device to an increased-power mode.

Abstract: Systems and methods for implementing an Energy-Efficient Ethernet (EEE) communication are provided. In some aspects, a method includes identifying an EEE signal configured to be communicated via a first set of wires. The method also includes processing the EEE signal such that the processed EEE signal is configured to be communicated via a second set of wires. The second set of wires including fewer wires than the first set of wires. The method also includes communicating the processed EEE signal via the second set of wires.

Abstract: In some aspects, the disclosure is directed to methods and systems for a device including a physical interface with electrical connection to a communication channel, and circuitry configured to detect energy received at the physical interface, wait a predetermined length of a time until the beginning of a time slot, monitor the physical interface during the time slot for a predefined pattern from the communication channel, and upon detection of the predefined pattern, transition the device to an increased-power mode.

Abstract: A circuit for power on data line (PoDL) injection includes a power source, a first and a second coupling component, and an interface. The power source provides one or more DC voltage levels. The first coupling component couples the power source to an interface for coupling to a transmission medium. An Ethernet device is coupled through the second coupling component to the interface. The first coupling component is a balanced component, and the Ethernet device is isolated from the power source via a pair of DC blocking capacitors connected between the first coupling component and the second coupling component.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Abstract: A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

Abstract: A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.