Abstract: A driver to drive a bus with a pullup and a pulldown transistor according to a data signal during a drive phase and to charge or discharge the bus to intermediate voltage levels during a precondition phase using the pullup and pulldown transistors, the driver comprising a buffer and latch to latch the bus voltage at the end of a drive phase; a precondition circuit responsive to the latch to switch ON a pullup transistor at the beginning of a precondition phase when the bus voltage was LOW in the previous drive phase so as to charge the bus voltage to a first voltage less than a supply voltage, and to switch ON a pulldown transistor at the beginning of the precondition phase when the bus voltage was HIGH in the previous drive phase so as to discharge the bus voltage to a second voltage above ground.

Abstract: A method and apparatus for processing saturation instructions in a computer system. A first logic device is coupled to receive at least one carry signal and generate an output signal in response to the carry signal. A second logic device is coupled to the first logic device. The second logic device is capable of selecting between a first plurality of input signals to generate an output signal. The output signal from the second logic device represents the result of the saturation instruction. A third logic device is coupled to the second logic device. The third logic device is coupled to receive a second plurality of input signals and generates an output signal. The second plurality of input signals include limit values corresponding to particular data formats.

Abstract: A processor having a circuit for performing a packed addition and/or packed subtraction operation. The decoder accesses the registers addressed by SRC1 and SRC2. These registers provide a first packed data and a second packed data to the circuit. Packed data consists of a number of fixed length data elements. The data elements can be eight bits, sixteen bits or thirty-two bits in length. The circuit performs the operation on the first data element from the first packed data and the first data element from second packed data, producing a first result data element. The circuit performs this operation on the next data element from the first packed data and the next data element from the second packed data, producing a next result data element. This continues for all the data elements in the first and second packed data. The result data elements constitute a result packed data that is stored in the destination register.

Abstract: A processor having a circuit for performing a packed addition and/or packed subtraction operation. The decoder accesses the registers addressed by SRC1 and SRC2. These registers provide a first packed data and a second packed data to the circuit. Packed data consists of a number of fixed length data elements. The data elements can be eight bits, sixteen bits or thirty-two bits in length. The circuit performs the operation on the first data element from the first packed data and the first data element from second packed data, producing a first result data element. The circuit performs this operation on the next data element from the first packed data and the next data element from the second packed data, producing a next result data element. This continues for all the data elements in the first and second packed data. The result data elements constitute a result packed data that is stored in the destination register.