Abstract: Intelligently loading legacy option ROMs in a computing system, including: generating, by a legacy option ROM manager, an inventory for the computing system, wherein the inventory for the computing system identifies one or more devices in the computing system; determining, by the legacy option ROM manager for each option ROM available for loading, whether a device supported by the option ROM is included in the inventory for the computing system; responsive to determining that the device supported by the option ROM is not included in the inventory for the computing system, preventing the option ROM from being loaded into an option ROM address space; and responsive to determining that the device supported by the option ROM is included in the inventory for the computing system, enabling the option ROM to be loaded into the option ROM address space.

Abstract: A computer node includes an integrated management module, a field-programmable gate array, and a plurality of individual hardware devices. The integrated management module receives a user identification and identifies an associated hardware configuration, wherein the hardware configuration identifies hardware devices to be powered off. The integrated management module may instruct the field-programmable gate array to use switches to power off the identified hardware devices without powering off other hardware devices.

Abstract: Methods, apparatuses, and computer program products for performing a boot sequence in a multi-processor system are provided. Embodiments include: in response to detecting initiation of a boot sequence of the multi-processor system, initializing, by a bootstrap processor (BSP), BSP memory associated with the BSP and initializing, by an application processor, memory associated with the application processor; determining, by the BSP, whether the initialization of the BSP memory is completed; and if the initialization of the BSP memory is completed, loading, by the BSP, an operating system on the BSP memory regardless of whether the application processor has completed initialization of the memory associated with the application processor.

Abstract: Dynamically updating firmware in a computing system, including: receiving, by a firmware update module, a request to update firmware in the computing system; receiving, by the firmware update module, a firmware update; storing, by the firmware update module, the firmware update into computer memory of the computing system; and initiating, by the firmware update module, a system management interrupt with the address in computer memory of the computing system at which the firmware update is stored.

Abstract: In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added.

Abstract: In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added.

Abstract: The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to applying user configurable options during bootstrap and provide a novel and non-obvious method, system and computer program product for user selectable configuration options application for inaccessible nonvolatile storage at bootstrap. In one embodiment of the invention, a method for user selectable configuration options application for inaccessible nonvolatile storage at bootstrap can be provided. The method can include powering up a motherboard for a computer system and reading user selectable configuration options for the computing system from sticky bits prior to bootstrap for the motherboard. The method further can include applying the user selectable configuration options to the computing system. Finally, the method can include performing bootstrap for the motherboard subsequent to applying the user selectable configuration options.

Abstract: The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to applying user configurable options during bootstrap and provide a novel and non-obvious method, system and computer program product for user selectable configuration options application for inaccessible nonvolatile storage at bootstrap. In one embodiment of the invention, a method for user selectable configuration options application for inaccessible nonvolatile storage at bootstrap can be provided. The method can include powering up a motherboard for a computer system and reading user selectable configuration options for the computing system from sticky bits prior to bootstrap for the motherboard. The method further can include applying the user selectable configuration options to the computing system. Finally, the method can include performing bootstrap for the motherboard subsequent to applying the user selectable configuration options.

Abstract: Removing building blocks from partitions to which they have been bound is disclosed. A building block of a platform is removed from a partition of the platform by first halting activity by the partition on the building block. A first partition identifier of the building block indicates the partition of the building block. The building block joined the partition in a masterless manner. The resources of the building block are withdrawn from the partition, and the building block is deauthorized from the platform.

Abstract: A masterless approach for binding building blocks to partitions is disclosed. Other blocks are first sent a first physical port identifier indicating a block's physical location, and a first partition identifier indicating the block's partition. Second physical port identifiers and second partition identifiers are received from the other blocks. The first physical port identifier and the second physical port identifiers of a subset of the other blocks are then sent to the subset, the second partition identifiers of the subset being equal to the first partition identifier. The first physical port identifier and the second physical port identifiers of the subset are also received from each block of the subset. A first logical port identifier indicating the block's logical location is sent to the subset, and second logical port identifiers are received from the subset. The block joins the partition indicated by the first partition identifier.

Abstract: Removing building blocks from partitions to which they have been bound is disclosed. A building block of a platform is removed from a partition of the platform by first halting activity by the partition on the building block. A first partition identifier of the building block indicates the partition of the building block. The building block joined the partition in a masterless manner. The resources of the building block are withdrawn from the partition, and the building block is deauthorized from the platform.

Abstract: A masterless approach for binding building blocks to partitions is disclosed. Other blocks are first sent a first physical port identifier indicating a block's physical location, and a first partition identifier indicating the block's partition. Second physical port identifiers and second partition identifiers are received from the other blocks. The first physical port identifier and the second physical port identifiers of a subset of the other blocks are then sent to the subset, the second partition identifiers of the subset being equal to the first partition identifier. The first physical port identifier and the second physical port identifiers of the subset are also received from each block of the subset. A first logical port identifier indicating the block's logical location is sent to the subset, and second logical port identifiers are received from the subset. The block joins the partition indicated by the first partition identifier.