Patents by Inventor Mehul Nagrani

Mehul Nagrani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Individual I/O modulation in memory devices
    Patent number: 7768846
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey P. Wright
  • INDIVIDUAL I/O MODULATION IN MEMORY DEVICES
    Publication number: 20080219067
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Application
    Filed: May 21, 2008
    Publication date: September 11, 2008
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey P. Wright
  • Individual I/O modulation in memory devices
    Patent number: 7388794
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey P. Wright
  • Individual I/O modulation in memory devices
    Publication number: 20060221671
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The out/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Application
    Filed: June 6, 2006
    Publication date: October 5, 2006
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey Wright
  • Individual I/O modulation in memory devices
    Patent number: 7082064
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: July 25, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey P. Wright
  • Individual I/O modulation in memory devices
    Publication number: 20050169068
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Application
    Filed: January 29, 2004
    Publication date: August 4, 2005
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey Wright