Abstract: The use of a netlist or other database containing topological information of an electrical circuit comprising a multiplicity of components which are to undergo safe operating area (SOA) checking, permits a relationship between recorded SOA errors to be established. Knowing how such errors may be interdependent can assist designers in deciding which errors should be rectified first. The relationship between the recorded errors relating to two connected components may be modified by a confidence factor based on elapsed time between the occurrence of the two recorded errors.

Abstract: In some embodiments, a substrate contact is formed by forming a first gate structure and a second gate structure. The first gate structure is formed in a first volume in a first area of the wafer and the second gate structure is formed in a second volume in a second area of the wafer. The gate dielectric is removed from the wafer in a first area of the wafer but remains in the second area. A first sidewall spacer formed for the gate structure and a second sidewall spacer is formed for the second gate structure. In some embodiments, the first gate structure can be utilized as a substrate contact and the second gate structure can be utilized as a gate of a transistor. In other embodiments, the first gate structure and the second gate structure can be removed and a metal gate material can be deposited in opening for forming a substrate contact and a metal gate, respectively.

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of the device using a device design, a device model and a simulation scenario; and one or more violation monitor for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule of the one or more violation rules during the executing the simulation of the device and, for each violation, determine information representing the respective violation, wherein the detecting the one or more violations comprises comparing a simulated parameter against a threshold.

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.

Abstract: The use of a netlist or other database containing topological information of an electrical circuit comprising a multiplicity of components which are to undergo safe operating area (SOA) checking, permits a relationship between recorded SOA errors to be established. Knowing how such errors may be interdependent can assist designers in deciding which errors should be rectified first. The relationship between the recorded errors relating to two connected components may be modified by a confidence factor based on elapsed time between the occurrence of the two recorded errors.

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determine information representing the respective violation, wherein detecting the one or more violations comprises comparing a simulated parameter against a threshold. The threshold controller is arranged to determine the threshold for the respective violation rule in dependence on a temporal characteristic of the associated violation.

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.

Abstract: A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device design for the second instantiation based on the layer of the second instantiation. identifying a first compare layer of the device design that comprises a plurality of first compare features including a first compared feature within the first region and a second compared feature within the second region, determining a difference between the first compared feature and the second compared feature, and determining if the difference meets a tolerance to determine if the first instantiation matches the second instantiation.

Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.

Abstract: A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.

Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: A semiconductor process and apparatus provide a T-shaped structure (84) formed from a polysilicon structure (10) and polysilicon spacers (80, 82) and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (100) of the T-shaped structure (84) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract: A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract: N channel and P channel transistors are enhanced by applying stressor layers of tensile and compressive, respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in deleterious effects when etching a contact hole at the interface between the two stressors. A contact to a gate is often preferably half way between N and P channel transistors which is also the seemingly best location for the border between the two stressor layers. The contact etch at the border can result in pitting of the underlying gate structure or in residual nitride in the contact hole. Therefore, it has been found beneficial to ensure that each contact is at least some predetermined distance from the stressor of the opposite type from the one the contact is passing through.

Abstract: A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.

Abstract: A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.

Abstract: A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer (20) is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer (22) is formed over the TEOS layer (20) and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer (20) before applying photoresist, pattern defects are reduced.

Abstract: Two conductors of the same layer are separated by a low-K dielectric to minimize capacitance between them. The first and second conductors may have sidewalls with conductive barriers. The conductive barriers are separated from the low-K dielectric by spacers. The dielectric spacers have a top portion and a lower portion in which the top portion may have a higher dielectric constant than the lower portion or may be the same material. The two conductors are formed in trenches in a convenient dielectric. Prior to forming the conductors, the conductive barriers are deposited in the trench. After the conductors are formed, the convenient dielectric is removed. The dielectric spacers are formed adjacent to the conductive barriers. The low-K dielectric is then deposited adjacent to the dielectric spacers and not in contact with the conductive barriers.

Abstract: Two conductors of the same layer are separated by a low-K dielectric to minimize capacitance between them. The first and second conductors may have sidewalls with conductive barriers. The conductive barriers are separated from the low-K dielectric by spacers. The dielectric spacers have a top portion and a lower portion in which the top portion may have a higher dielectric constant than the lower portion or may be the same material. The two conductors are formed in trenches in a convenient dielectric. Prior to forming the conductors, the conductive barriers are deposited in the trench. After the conductors are formed, the convenient dielectric is removed. The dielectric spacers are formed adjacent to the conductive barriers. The low-K dielectric is then deposited adjacent to the dielectric spacers and not in contact with the conductive barriers.