Abstract: The present disclosure illustrates an image sensor. The image sensor includes an image sensing array and a voltage supply array. The image sensing array and the voltage supply array are coupled to an analog-to-digital converter array. The image sensing array captures image data. The image sensing array supports one of a rolling shutter mechanism and a global shutter mechanism according to setting. The voltage supply array includes a plurality of voltage supply circuits to supply dummy voltage. During an auto-zero period, the voltage supply array provides the dummy voltage to the analog-to-digital converter array. Pluralities of comparators of the analog-to-digital converter array execute an auto-zero function based on the dummy voltage. After finishing the auto-zero function, the image sensing array outputs the image data to the analog-to-digital converter array. The analog-to-digital converter array makes the image data be digital.

Abstract: A method for reducing fixed pattern noise of an image sensor is provided. The method includes: accessing pixel data of at least one test frame in a test environment; and calculating/deriving average values of each column based on at least one portion of pixel data of the column in the at least one test frame, wherein the average values of columns are used as calibration values for calibrating image pixel data of columns when the image sensor operates in a normal light source environment.

Abstract: The present invention provides an image sensor circuit with a power noise filtering function and a control method thereof. The image sensor circuit includes: an image sensing unit, for sensing an image, to generate an image sensed signal; a power noise sensing unit, for sensing a power noise, to generate a power noise signal; a differential amplifier circuit, which is coupled to the image sensing unit and the power noise sensing unit, for receiving the image sensed signal and the power noise signal, to generate a differential filtered signal by a differential amplification operation between the image sensed signal and the power noise signal; and an analog-to-digital converter (ADC) circuit, which is coupled to the differential amplifier circuit, for receiving the differential filtered signal, to generate a digital image signal.

Abstract: The present disclosure illustrates an image sensor. The image sensor includes an image sensing array and a voltage supply array. The image sensing array and the voltage supply array are coupled to an analog-to-digital converter array. The image sensing array captures image data. The image sensing array supports one of a rolling shutter mechanism and a global shutter mechanism according to setting. The voltage supply array includes a plurality of voltage supply circuits to supply dummy voltage. During an auto-zero period, the voltage supply array provides the dummy voltage to the analog-to-digital converter array. Pluralities of comparators of the analog-to-digital converter array execute an auto-zero function based on the dummy voltage. After finishing the auto-zero function, the image sensing array outputs the image data to the analog-to-digital converter array. The analog-to-digital converter array makes the image data be digital.

Abstract: A method for reducing fixed pattern noise of an image sensor is provided. The method includes: accessing pixel data of at least one test frame in a test environment; and calculating/deriving average values of each column based on at least one portion of pixel data of the column in the at least one test frame, wherein the average values of columns are used as calibration values for calibrating image pixel data of columns when the image sensor operates in a normal light source environment.

Abstract: The present invention provides an image sensor circuit with a power noise filtering function and a control method thereof. The image sensor circuit includes: an image sensing unit, for sensing an image, to generate an image sensed signal; a power noise sensing unit, for sensing a power noise, to generate a power noise signal; a differential amplifier circuit, which is coupled to the image sensing unit and the power noise sensing unit, for receiving the image sensed signal and the power noise signal, to generate a differential filtered signal by a differential amplification operation between the image sensed signal and the power noise signal; and an analog-to-digital converter (ADC) circuit, which is coupled to the differential amplifier circuit, for receiving the differential filtered signal, to generate a digital image signal.

Abstract: The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal.

Abstract: Network interface apparatus with power management is disclosed, which comprises a physical layer circuit, for receiving a packet on a network; a media access control circuit, for performing the media access processing on the packet to output a processed packet; an interface circuit, coupled to the media access control layer, for transmitting the processed packet to a bus; a detecting circuit, coupled to the physical layer circuit, for detecting a transmitting status of the packet on the network to output a detecting signal; a loading control circuit, coupled to the detecting circuit, for controlling a load positioned in the interface circuit according to the detecting signal.

Abstract: A temperature sensing apparatus disposed inside a chip includes first and second current generation circuits, first and second current-to-frequency converters, and a counting unit. The first current generation circuit is configured to generate a first current varying proportional to the temperature of the temperature sensing apparatus. The second current generation circuit is configured to generate a second current independent of temperature. The first current-to-frequency converter is configured to generate a first frequency signal with a first frequency indicative of the first current, and the second current-to-frequency converter is configured to generate a second frequency signal with a second frequency indicative of the second current. The counting unit is configured to generate a digital signal indicative of the temperature according to the difference between the first and second frequencies.

Abstract: A data transmitting and receiving device and method are used for saving powers and maintaining the connection quality, stability and continuous link. The method includes the step of gradually adjusting the de-emphasis of the signal transmitted from the data transmitting and receiving device according to the setting value thereof. The method also includes the steps of transmitting training sequence signal with an amplitude and the default de-emphasis by the data transmitting and receiving device to the remote device, receiving the training sequence signal from the remote device, thereby the channel attenuation is estimated using the method, and a better de-emphasis is set up. Then, the data transmitting and receiving device gradually increases the amplitude of the training sequence signal and re-transmits it until the remote device receives the training sequence signal transmitted therefrom.

Abstract: The disclosure is a device and a method for receiver-equalizer calibration, in which the device includes an adaptive filter, a Clock Data Recovery (CDR) unit, an adaptive control unit and a run length encoding unit. The adaptive filter receives a channel signal, calibrates the channel signal according to a filter control signal and compensates the channel signal to obtain a compensative signal. The CDR unit receives the compensative signal to generate a sampling clock signal, a data signal and a transition sampling signal. The run length encoding unit receives the data signal and run-length encodes the data signal to generate first code data and second code data. The adaptive control unit receives the first code data, the second code data, the data signal and the transition sampling signal, and performs weight calculation to adjust the filter control signal.

Abstract: A temperature sensing apparatus disposed inside a chip includes first and second current generation circuits, first and second current-to-frequency converters, and a counting unit. The first current generation circuit is configured to generate a first current varying proportional to the temperature of the temperature sensing apparatus. The second current generation circuit is configured to generate a second current independent of temperature. The first current-to-frequency converter is configured to generate a first frequency signal with a first frequency indicative of the first current, and the second current-to-frequency converter is configured to generate a second frequency signal with a second frequency indicative of the second current. The counting unit is configured to generate a digital signal indicative of the temperature according to the difference between the first and second frequencies.

Abstract: The disclosure is a device and a method for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, which includes a CDR unit and a weight calculator unit. The CDR unit receives a compensative signal of an equalization filter to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal. The weight calculator unit receives the error signal, the transition sampling signal and the data signal, and then uses a run length technique to generate weight data. The weight data controls a voltage control oscillator (VCO) which calibrates the phase and the frequency of the sampling clock signal.

Abstract: The disclosure is a device and a method for receiver-equalizer calibration, in which the device includes an adaptive filter, a Clock Data Recovery (CDR) unit, an adaptive control unit and a run length encoding unit. The adaptive filter receives a channel signal, calibrates the channel signal according to a filter control signal and compensates the channel signal to obtain a compensative signal. The CDR unit receives the compensative signal to generate a sampling clock signal, a data signal and a transition sampling signal. The run length encoding unit receives the data signal and run-length encodes the data signal to generate first code data and second code data. The adaptive control unit receives the first code data, the second code data, the data signal and the transition sampling signal, and performs weight calculation to adjust the filter control signal.

Abstract: A data transmitting and receiving device and method are used for saving powers and maintaining the connection quality, stability and continuous link. The method includes the step of gradually adjusting the de-emphasis of the signal transmitted from the data transmitting and receiving device according to the setting value thereof. The method also includes the steps of transmitting training sequence signal with an amplitude and the default de-emphasis by the data transmitting and receiving device to the remote device, receiving the training sequence signal from the remote device, thereby the channel attenuation is estimated using the method, and a better de-emphasis is set up. Then, the data transmitting and receiving device gradually increases the amplitude of the training sequence signal and re-transmits it until the remote device receives the training sequence signal transmitted therefrom.

Abstract: Network interface apparatus with power management is disclosed, which comprises a physical layer circuit, for receiving a packet on a network; a media access control circuit, for performing the media access processing on the packet to output a processed packet; an interface circuit, coupled to the media access control layer, for transmitting the processed packet to a bus; a detecting circuit, coupled to the physical layer circuit, for detecting a transmitting status of the packet on the network to output a detecting signal; a loading control circuit, coupled to the detecting circuit, for control a load positioned in the interface circuit according to the detecting signal.

Abstract: An apparatus comprises a first stage, a second stage, and a switch circuit. The first stage and the second stage are coupled between a first reference voltage and a second reference voltage. The first stage has a first input end for receiving an input signal and a first output end for outputting a first output signal. The second stage has a second input end for receiving the first output signal from the first output end of the first stage and a second output end for outputting a second output signal. The switch circuit is coupled between the second stage and at least one of the first reference voltage and the second reference voltage for receiving a power control signal and for turning on or turning off according to the power control signal such that the current leakage of the second stage is reduced.

Abstract: A traveling-wave switch includes a FET-integrated Coplanar Waveguide (CPW) line structure. The FET-integrated CPW line structure incorporates a transistor, a signal line, and the ground, that can be used to eliminate the limitations imposed by the parasitic inductance of the prior art on the operation frequency of the switch. The signal line is connected directly to the drain of the transistor, eliminating the parasitic inductance caused by the connection wire between the signal line and the transistor. The source of the transistor is coupled directly to the ground of the coplanar waveguide line, thus eliminating the parasitic inductance between the transistor and ground, and raising the operation frequency of the switch.

Abstract: A traveling-wave switch having a FET-integrated Coplanar Waveguide (CPW) line structure. The newly designed FET-integrated CPW line structure incorporating a transistor, a signal line, and the ground, that can be used to eliminate the limitations imposed by the parasitic inductance of the prior art on the operation frequency of the switch. The traveling-wave switch having a FET-integrated CPW line structure can be utilized to effectively raise its operation frequency and reduce its chip size. By reducing the chip size, the new design utilizing the standard GaAs HEMT MMIC process can be used to reduce the production cost of the traveling-wave switch.