Patents by Inventor Mei-Chen Lee

Mei-Chen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387749
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
  • Publication number: 20240347645
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
  • Patent number: 12113135
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan
  • Patent number: 12051755
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan
  • Patent number: 10607856
    Abstract: A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.
    Type: Grant
    Filed: June 18, 2017
    Date of Patent: March 31, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Kun-Yung Huang, Chih-Fu Lung, Shih-Chi Li, Mei-Chen Lee, Chung-Hao Tsai, Chi-Liang Wang
  • Publication number: 20180366344
    Abstract: A manufacturing method of a redistribution layer is provided. The method includes the following steps. A patterned sacrificial layer is formed on a carrier. An actuate angle is formed between a side wall of the patterned sacrificial layer and the carrier. A first conductive layer is formed. The first conductive layer includes a plurality of first portions formed on the carrier and a plurality of second portions formed on the patterned sacrificial layer. The patterned sacrificial layer and the second portions of the first conductive layer are removed from the carrier. Another manufacturing method of a redistribution layer is also provided.
    Type: Application
    Filed: June 18, 2017
    Publication date: December 20, 2018
    Applicant: Powertech Technology Inc.
    Inventors: Kun-Yung Huang, Chih-Fu Lung, Shih-Chi Li, Mei-Chen Lee, Chung-Hao Tsai, Chi-Liang Wang
  • Publication number: 20160120273
    Abstract: The invention is directed to a non-piercing earring comprising a front member, a rear member, a first magnet, a second magnet, a stop, and a compressible spring. The front member and rear member connect to form a hoop shaped earring. The rear member slides within an inner cavity in the front member. The inner cavity houses a compressible spring to generate a force pushing the rear member toward the user's ear. The terminable ends of the front member and rear member have magnets situated to provide an attractive force and further maintain the earring on the ear of the user.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 5, 2016
    Inventor: Mei Chen Lee
  • Patent number: 6443530
    Abstract: A vehicle wheel ideal for buggy, stroller, carriage, tricycle, dolly buggy, and the like, having a wheel rim mounted on a wheel axle and holding an outer tire, movable parts mounted on an inner table suspended in the wheel rim, and a cartoon-Figured wheel cover fixedly fastened to the inner table. When the vehicle goes forward, the cartoon Figured wheel cover doesn't move at all, on the contrary, the Figure's eyes, nose, and ears start to swing.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: September 3, 2002
    Inventor: Mei-Chen Lee