Patents by Inventor Mei Chin Ng
Mei Chin Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11081417Abstract: A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.Type: GrantFiled: July 17, 2019Date of Patent: August 3, 2021Assignee: Infineon Technologies AGInventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Soon Lock Goh, Swee Kah Lee, Joachim Mahler, Mei Chin Ng, Beng Keh See, Guan Choon Matthew Nelson Tee
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Publication number: 20200006267Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Inventors: Swee Kah Lee, Hock Heng Chong, Mei Chin Ng, Aileen Manantan Soriano, Fong Mei Lum, Muhammad Muhammat Sanusi, Soon Lock Goh
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Patent number: 10490470Abstract: A method of fabricating a semiconductor package comprises providing a carrier, fabricating an opening in the carrier, attaching a semiconductor chip to the carrier and fabricating an encapsulation body covering the semiconductor chip.Type: GrantFiled: December 12, 2017Date of Patent: November 26, 2019Assignee: Infineon Technologies AGInventors: Hock Heng Chong, Sook Woon Chan, Chau Fatt Chiang, Khar Foong Chung, Chee Hong Fang, Muhammat Sanusi Muhammad, Mei Chin Ng, Yean Seng Ng, Pei Luan Pok, Choon Huey Wang
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Publication number: 20190341324Abstract: A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.Type: ApplicationFiled: July 17, 2019Publication date: November 7, 2019Inventors: Sook Woon CHAN, Chau Fatt CHIANG, Kok Yau CHUA, Soon Lock GOH, Swee Kah LEE, Joachim MAHLER, Mei Chin NG, Beng Keh SEE, Guan Choon Matthew Nelson TEE
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Patent number: 10431560Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.Type: GrantFiled: October 11, 2017Date of Patent: October 1, 2019Assignee: Infineon Technologies AGInventors: Swee Kah Lee, Hock Heng Chong, Mei Chin Ng, Aileen Manantan Soriano, Fong Mei Lum, Muhammad Muhammat Sanusi, Soon Lock Goh
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Patent number: 10396007Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.Type: GrantFiled: March 2, 2017Date of Patent: August 27, 2019Assignee: Infineon Technologies AGInventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Soon Lock Goh, Swee Kah Lee, Joachim Mahler, Mei Chin Ng, Beng Keh See, Guan Choon Matthew Nelson Tee
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Publication number: 20180174935Abstract: A method of fabricating a semiconductor package comprises providing a carrier, fabricating an opening in the carrier, attaching a semiconductor chip to the carrier and fabricating an encapsulation body covering the semiconductor chip.Type: ApplicationFiled: December 12, 2017Publication date: June 21, 2018Inventors: Hock Heng CHONG, Sook Woon CHAN, Chau Fatt CHIANG, Khar Foong CHUNG, Chee Hong FANG, Muhammat Sanusi MUHAMMAD, Mei Chin NG, Yean Seng NG, Pei Luan POK, Choon Huey WANG
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Publication number: 20180033752Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.Type: ApplicationFiled: October 11, 2017Publication date: February 1, 2018Inventors: Swee Kah Lee, Hock Heng Chong, Mei Chin Ng, Aileen Manantan Soriano, Fong Mei Lum, Muhammad Muhammat Sanusi, Soon Lock Goh
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Patent number: 9806043Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads are also embedded in the mold compound and electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.Type: GrantFiled: March 3, 2016Date of Patent: October 31, 2017Assignee: Infineon Technologies AGInventors: Swee Kah Lee, Hock Heng Chong, Mei Chin Ng, Aileen Manantan Soriano, Fong Mei Lum, Muhammad Muhammat Sanusi, Soon Lock Goh
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Publication number: 20170256509Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads are also embedded in the mold compound and electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.Type: ApplicationFiled: March 3, 2016Publication date: September 7, 2017Inventors: Swee Kah Lee, Hock Heng Chong, Mei Chin Ng, Aileen Manantan Soriano, Fong Mei Lum, Muhammad Muhammat Sanusi, Soon Lock Goh
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Publication number: 20170256472Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.Type: ApplicationFiled: March 2, 2017Publication date: September 7, 2017Inventors: Sook Woon CHAN, Chau Fatt CHIANG, Kok Yau CHUA, Soon Lock GOH, Swee Kah LEE, Joachim MAHLER, Mei Chin NG, Beng Keh SEE, Guan Choon Matthew Nelson TEE
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Patent number: 9475691Abstract: A semiconductor package includes an electrically conductive lead-frame, including a first die paddle having a first opening, and a plurality of electrically conductive leads, a ridge formed around a perimeter of the first opening, and an electrically insulating molding compound. The electrically insulating molding compound includes an interior cavity being defined by a planar base surface and outer sidewalls, a second opening formed in the base surface, and an interior sidewall within the interior cavity. The molding compound is formed around the lead-frame with the first die paddle in the interior cavity. The first and second openings are aligned with one another so as to form a port that provides access to the interior cavity. The ridge and the interior sidewall form a dam that is configured to collect liquefied sealant and prevent the liquefied sealant from overflowing into the port or into adjacent regions of the interior cavity.Type: GrantFiled: June 26, 2015Date of Patent: October 25, 2016Assignee: Infineon Technologies AGInventors: Kok Yau Chua, Sook Woon Chan, Chau Fatt Chiang, Stefan Martens, Matthias Steiert, Kian Hong Yeo, Hock Siang Chua, Mei Chin Ng, Swee Kah Lee
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Patent number: 9219025Abstract: A molded flip-chip semiconductor package includes a leadframe having opposing first and second main surfaces, a first metallization on the first main surface, a second metallization on the second main surface, recessed regions which extend from the second main surface toward the first main surface, and spaced apart leads chemically etched into the leadframe between gaps in the first metallization. The package further includes a semiconductor die having a plurality of pads facing and attached to the leads of the leadframe, a first molding compound that fills the recessed regions, and a second molding compound that encases the semiconductor die and fills the space between the leads such that the second molding compound abuts the first molding compound. A is the overall thickness of the leadframe, B is the spacing between adjacent ones of the leads, and B/A<1.Type: GrantFiled: August 15, 2014Date of Patent: December 22, 2015Assignee: Infineon Technologies AGInventors: Swee Kah Lee, Chee Hong Fang, Mei Chin Ng
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Patent number: 8951841Abstract: In one embodiment, a semiconductor package includes a clip frame with a first clip having a first support structure, a first lever, and a first contact portion, which is disposed on a front side of the semiconductor package. The first support structure is adjacent an opposite back side of the semiconductor package. The first lever joins the first contact portion and the first support structure. A first die is disposed over the first support structure of the first clip. The first die has a first contact pad on the front side of the semiconductor package. An encapsulant material surrounds the first die and the first clip.Type: GrantFiled: March 20, 2012Date of Patent: February 10, 2015Assignee: Infineon Technologies AGInventors: Melissa Mei Ching Ng, Mei Chin Ng, Peng Soon Lim
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Publication number: 20130249067Abstract: In one embodiment, a semiconductor package includes a clip frame with a first clip having a first support structure, a first lever, and a first contact portion, which is disposed on a front side of the semiconductor package. The first support structure is adjacent an opposite back side of the semiconductor package. The first lever joins the first contact portion and the first support structure. A first die is disposed over the first support structure of the first clip. The first die has a first contact pad on the front side of the semiconductor package. An encapsulant material surrounds the first die and the first clip.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Applicant: Infineon Technologies AGInventors: Melissa Mei Ching Ng, Mei Chin Ng, Peng Soon Lim