Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Abstract: A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.

Abstract: An adapter element, a conversion apparatus and a conversion method are applied in an electrical connection between a memory element and an electronic apparatus for transmitting data. The switch apparatus includes a first interface, a second interface and a processor. A first adapter element is inserted into the first interface. A second adapter element is inserted into the second interface. When the memory element or the electronic apparatus is replaced, the first adapter element or the second adapter element is also replaced. The processor then detects formats for the first adapter element and the second adapter element to perform format conversions in transmitting data between the first interface and the second interface. Therefore, the conversion apparatus could support different memory elements or different electronic apparatuses.

Abstract: Magic Packet technique is developed to remotely awake a computer host in a sleeping mode on a node through computer network. Instead of utilizing a large amount of memory or a complex algorithm, an algorithm and system, which only utilize two sets of counters and control logics to perfectly detect the Magic Packet according to the characteristics of magic packet are disclosed. According to the present invention, if a LAN controller on a node of the network is in magic packet mode, it will detect all input frames addressed in the node to search a specific data sequence indicative of the Magic Packet frame. Once the controller detects the data sequence, it will notice the power management circuitry of the computer host on the sleeping node to awake the system.