Abstract: A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.

Abstract: The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions.

Abstract: The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions.

Abstract: A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions.

Abstract: Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages.

Abstract: A flash or block erase electrically erasable programmable read-only memory (EEPROM) cell (10) includes a substrate (12) having a channel region (22), and a source (28) and a drain (32) formed in the substrate (12) on opposite sides of the channel region (22). A first oxide layer (19), a floating gate (20), a second oxide layer (24) and a control gate (26) are formed over the channel region (22). The cell (10) is programmed by hot electron injection from the drain (32) into the floating gate (20), and erased by Fowler-Nordheim tunneling from the floating gate (20) to the source (28). A gap (36) is provided between a sidewall (20a) of the floating gate (20) and the drain (32) to increase the electric field in the drain depletion region. An oxide sidewall spacer (38) is formed on the first oxide layer (19) in the gap (36) which traps electrons.

Abstract: Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floating gate (34) further has an erase section (34b) which extends from the program section (34a) around an end of a channel (22) to the source (18). A thin tunnel oxide layer (32) is formed between an end portion (34c) of the erase section (34b) and an underlying portion of the source (18) which enables the floating gate (34) to be erased by Fowler-Nordheim tunneling from the end portion (34c) through the oxide layer (32) to the source (18) with low applied voltages.

Abstract: Highly doped N- and P-type wells (16a, 16b) in a first silicon layer (16) on an insulator layer (14) of a SIMOX substrate (10). Complementary MOSFET devices (52,54,58,62) are formed in lightly doped N- and P-type active areas (22a, 22b) in a second silicon layer (22) formed on the first silicon layer (16). Adjacent active areas (22a, 22b) and underlying wells (16a, 16b) are isolated from each other by trenches (36,78) filled with a radiation-hard insulator material. Field oxide layers (42,64) are formed of a radiation-hard insulator material, preferably boron phosphorous silicon dioxide glass, over the surface of the second silicon layer (22) except in contact areas (68) of the devices (52,54,58,62). The devices (52,54,58,62) are formed in the upper portions of the active areas (22a, 22b), and are insensitive to the interfacial states of the SIMOX substrate (10).