Patents by Inventor Mei Fen Hiew

Mei Fen Hiew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105564
    Abstract: A semiconductor package includes: a semiconductor die attached to a leadframe and having a first bond pad at a side of the semiconductor die facing away from the leadframe; a metal clip having a first bonding region attached to the first bond pad of the semiconductor die by a plurality of first wire bonds which extend through a plurality of first openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die; and a joint between the plurality of first wire bonds and the metal clip at a side of the metal clip facing away from the semiconductor die. Additional semiconductor package embodiments and related methods of manufacture are also described.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Inventors: Mohd Kahar Bajuri, Joel Feliciano Del Rosario, Thai Kee Gan, Mohd Afiz Hashim, Mei Fen Hiew
  • Patent number: 11842953
    Abstract: A method of attaching a metal clip to a semiconductor die includes: aligning a first bonding region of the metal clip with a first bond pad of the semiconductor die; and while the first bonding region of the metal clip is aligned with the first bond pad of the semiconductor die, forming a plurality of first wire bonds to the first bond pad of the semiconductor die through a plurality of openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die. Additional methods and related semiconductor packages produced from such methods are also described.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: December 12, 2023
    Assignee: Infineon Technologies AG
    Inventors: Mohd Kahar Bajuri, Joel Feliciano Del Rosario, Thai Kee Gan, Mohd Afiz Hashim, Mei Fen Hiew
  • Publication number: 20230298956
    Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 21, 2023
    Applicant: Infineon Technologies AG
    Inventors: Chii Shang HONG, Li Fong CHONG, Yee Beng DARYL YEOW, Edward FÜRGUT, Mei Fen HIEW, Azlina KASSIM, Ralf OTREMBA, Bernd SCHMOELZER, Joon Shyan TAN, Lee Shuang WANG
  • Patent number: 11621204
    Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: April 4, 2023
    Assignee: Infineon Technologies AG
    Inventors: Oliver Markus Kreiter, Ludwig Busch, Angel Enverga, Mei Fen Hiew, Tian See Hoe, Elvis Keli, Kean Ming Koe, Sanjay Kumar Murugan, Michael Niendorf, Ivan Nikitin, Bernhard Stiller, Thomas Stoek, Ke Yan Tean
  • Publication number: 20220352056
    Abstract: A method of attaching a metal clip to a semiconductor die includes: aligning a first bonding region of the metal clip with a first bond pad of the semiconductor die; and while the first bonding region of the metal clip is aligned with the first bond pad of the semiconductor die, forming a plurality of first wire bonds to the first bond pad of the semiconductor die through a plurality of openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die. Additional methods and related semiconductor packages produced from such methods are also described.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Inventors: Mohd Kahar Bajuri, Joel Feliciano Del Rosario, Thai Kee Gan, Mohd Afiz Hashim, Mei Fen Hiew
  • Publication number: 20220262693
    Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.
    Type: Application
    Filed: February 17, 2021
    Publication date: August 18, 2022
    Inventors: Oliver Markus Kreiter, Ludwig Busch, Angel Enverga, Mei Fen Hiew, Tian See Hoe, Elvis Keli, Kean Ming Koe, Sanjay Kumar Murugan, Michael Niendorf, Ivan Nikitin, Bernhard Stiller, Thomas Stoek, Ke Yan Tean
  • Publication number: 20210043549
    Abstract: A clip for a semiconductor package includes a first portion and a second portion. The first portion includes a first surface, a second surface opposite to the first surface and configured to contact a first electrically conductive component, and a stepped region between the first surface and the second surface such that the second surface has a smaller area than the first surface. The second portion is coupled to the first portion and configured to contact a second electrically conductive component. The second portion includes a third surface aligned with the first surface.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 11, 2021
    Applicant: Infineon Technologies AG
    Inventors: Ke Yan Tean, Mei Fen Hiew, Jia Yi Wong