Patents by Inventor Mei Hsu Wong
Mei Hsu Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940822Abstract: A semiconductor device includes an analog voltage regulator and an integrated circuit module. The analog voltage regulator generates a regulated output voltage. The integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (DVOC). The first sensor generates a digital reference voltage based on an analog reference voltage. The second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. The DVOC generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. The regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.Type: GrantFiled: May 26, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
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Publication number: 20240012969Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.Type: ApplicationFiled: June 5, 2023Publication date: January 11, 2024Inventors: Haohua Zhou, Tze-Chiang Huang, Mei Hsu Wong
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Publication number: 20230366917Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
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Publication number: 20230343754Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
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Patent number: 11740272Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.Type: GrantFiled: April 21, 2021Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
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Patent number: 11735565Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.Type: GrantFiled: December 28, 2020Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
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Publication number: 20230261572Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Alan Roth, Haohua Zhou, Eric Soenen, Ying-Chih Hsu, Paul Ranucci, Mei Hsu Wong, Tze-Chiang Huang
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Patent number: 11671010Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.Type: GrantFiled: August 12, 2020Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alan Roth, Haohua Zhou, Eric Soenen, Ying-Chih Hsu, Paul Ranucci, Mei Hsu Wong, Tze-Chiang Huang
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Patent number: 11669664Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.Type: GrantFiled: April 5, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haohua Zhou, Tze-Chiang Huang, Mei Hsu Wong
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Publication number: 20220413527Abstract: A semiconductor device includes an analog voltage regulator and an integrated circuit module. The analog voltage regulator generates a regulated output voltage. The integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (DVOC). The first sensor generates a digital reference voltage based on an analog reference voltage. The second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. The DVOC generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. The regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.Type: ApplicationFiled: May 26, 2022Publication date: December 29, 2022Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
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Publication number: 20220292237Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Yuan TING, Hsin-Cheng Chen, Sandeep Kumar Goel, Mei Hsu Wong, Yun-Han Lee
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Publication number: 20220037288Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.Type: ApplicationFiled: December 28, 2020Publication date: February 3, 2022Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
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Publication number: 20210373057Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.Type: ApplicationFiled: April 21, 2021Publication date: December 2, 2021Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
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Publication number: 20210249952Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.Type: ApplicationFiled: August 12, 2020Publication date: August 12, 2021Inventors: Alan Roth, Haohua Zhou, Eric Soenen, Ying-Chih Hsu, Paul Ranucci, Mei Hsu Wong, Tze-Chiang Huang
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Publication number: 20210224445Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Haohua Zhou, Tze-Chiang Huang, Mei Hsu Wong
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Patent number: 10970439Abstract: A System On Chip (SOC) current profile model for Integrated Voltage Regulator (IVR) co-design may be provided. A first current profile model may be extracted corresponding to an SOC at a first design stage of the SOC. Then it may be determined that an IVR and the SOC pass a first co-simulation based on the extracted first current profile model. Next, a second current profile model may be extracted corresponding to the SOC at a second design stage of the SOC. Then it may be determined that the IVR and the SOC pass a second co-simulation based on the extracted second current profile model. A third current profile model may be extracted corresponding to the SOC at a third design stage of the SOC. Then it may be determined that the IVR and the SOC pass a third co-simulation based on the extracted third current profile model.Type: GrantFiled: October 11, 2019Date of Patent: April 6, 2021Inventors: Haohua Zhou, Tze-Chiang Huang, Mei Hsu Wong
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Publication number: 20200175129Abstract: A System On Chip (SOC) current profile model for Integrated Voltage Regulator (IVR) co-design may be provided. A first current profile model may be extracted corresponding to an SOC at a first design stage of the SOC. Then it may be determined that an IVR and the SOC pass a first co-simulation based on the extracted first current profile model. Next, a second current profile model may be extracted corresponding to the SOC at a second design stage of the SOC. Then it may be determined that the IVR and the SOC pass a second co-simulation based on the extracted second current profile model. A third current profile model may be extracted corresponding to the SOC at a third design stage of the SOC. Then it may be determined that the IVR and the SOC pass a third co-simulation based on the extracted third current profile model.Type: ApplicationFiled: October 11, 2019Publication date: June 4, 2020Inventors: Haohua Zhou, Tze-Chiang Huang, Mei Hsu Wong