Abstract: A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5F6, BCl3, Br2, HF, HCl, HBr, HI, and NF3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

Abstract: A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5F6, BCl3, Br2, HF, HCl, HBr, HI, and NF3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

Abstract: A method is disclosed for forming dual damascene structures with a multi-purpose composite mask. The composite mask serves not only to prevent via poisoning, but also to improve the lithographic characteristics of forming a dual damascene structure. This is accomplished by using a mask comprising silicon-based as well as polymeric dielectric layers. Thus, one of the components of the composite mask, namely, the polymeric dielectric, makes it possible to protect the via openings by conformally covering the sidewalls of the via and, at the same time, by bringing controllability to the height of the protective dielectric in the via opening. In addition, because the polymeric dielectric also serves as the main plasma resisting layer during the trench etch, the required photoresist is much thinner; therefore, the lithography process window can be extended beneficially.

Abstract: An improved and new process for photoresist stripping for use during fabrication of semiconductor integrated circuits, which use porous low-k dielectric materials, such as OSG or HSQ, as the interlevel and intra-level insulating layers, has been developed. Photoresist stripping in microwave or rf generated plasmas in gaseous mixtures of NH3 and CO takes place without attack or damage to underlying layers of OSG or HSQ. Optimum results are obtained when the ratio of CO to NH3 is between about 0.8 and 1.2.

Abstract: Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed an etch stop layer interposed between a first dielectric layer and second dielectric layer within a non active product region of a substrate, but not within an active product region of the substrate. Within the dual damascene method, an endpoint for forming a trench within a dual damascene aperture within the active product region is sensed by reaching the etch stop layer when forming a dummy trench within the non active product region.

Abstract: Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed an etch stop layer interposed between a first dielectric layer and second dielectric layer within a non active product region of a substrate, but not within an active product region of the substrate. Within the dual damascene method, an endpoint for forming a trench within a dual damascene aperture within the active product region is sensed by reaching the etch stop layer when forming a dummy trench within the non active product region.

Abstract: Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a bottom etch stop layer formed of a first material and an intermediate etch stop layer formed as a laminate of a second material having formed thereupon a third material. Within the method, the second material serves as an etch stop for the first material and the third material, which may be identical materials. Within the method, there may be etched completely through the bottom etch stop layer to reach a contact region formed there beneath while not etching completely through the intermediate etch stop layer to reach a first dielectric layer formed there beneath.

Abstract: A method and a structure for protecting a work piece in a semiconductor manufacturing process includes a cassette for mounting therein the work pieces and a sheet piece for shielding the work pieces; and a working platform for mounting thereon said cassette. Furthermore, there is a lid covering the working platform in order to prevent a contaminant from entering the cassette during the semiconductor manufacturing process so that the gate oxide loss of every wafer in the cassette will be reduced.

Abstract: A vapor processing method for reducing oxide material depletion includes an early step of placing a polymer-coated substrate inside a vapor process chamber (VPC), a pre-processing step of passing an inert gas into the VPC for a definite period followed by an idling period, a clearing step of passing a reactive gas carried by an inert carrier into the VPC for clearing away previously deposited polymer on the substrate, and a post-processing step of passing an inert gas into the VPC to purge any unreacted reactive gases. Thereafter, the substrate is transferred to a dry task chamber (DTC) for cleaning, wherein the cleaning includes removing any residual gases on the wafer surface. Time required for cleaning the wafer in the DTC is smaller than the total time required for pre-processing, polymer clearing and post-processing.