Abstract: A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.

Abstract: A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.

Abstract: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.

Abstract: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.

Abstract: A computer implemented method for estimating manufacturing target bias for products in manufacturing tools. The method first establishes a first data set according to manufacturing target bias history based on a correlation with tools used. The manufacturing tools comprise a first manufacturing tool and other manufacturing tools. Next, a testing operation is executed for a predicted product in the first manufacturing tool to obtain a first predicted manufacturing target bias. Finally, manufacturing target bias of the predicted product in the other manufacturing tools is calculated according to the first data set and the first predicted manufacturing target bias.

Abstract: A computer implemented method for estimating manufacturing target bias for products in manufacturing tools. The method first establishes a first data set according to manufacturing target bias history based on a correlation with tools used. The manufacturing tools comprise a first manufacturing tool and other manufacturing tools. Next, a testing operation is executed for a predicted product in the first manufacturing tool to obtain a first predicted manufacturing target bias. Finally, manufacturing target bias of the predicted product in the other manufacturing tools is calculated according to the first data set and the first predicted manufacturing target bias.