Patents by Inventor Mei Lan GUO
Mei Lan GUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11889686Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.Type: GrantFiled: September 7, 2021Date of Patent: January 30, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Miao Shen, Li Hong Xiao, Yushi Hu, Qian Tao, Mei Lan Guo, Yong Zhang, Jian Hua Sun
-
Publication number: 20240032293Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.Type: ApplicationFiled: September 28, 2023Publication date: January 25, 2024Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Publication number: 20230255025Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Patent number: 11690219Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.Type: GrantFiled: May 27, 2021Date of Patent: June 27, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Patent number: 11581322Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs, a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack, a TAC extending vertically through the conductor/dielectric layer pairs in the memory stack, and a dummy channel structure filled with a dielectric layer and extending vertically through the conductor/dielectric layer pairs in the memory stack.Type: GrantFiled: November 21, 2020Date of Patent: February 14, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Patent number: 11532636Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.Type: GrantFiled: November 30, 2020Date of Patent: December 20, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Publication number: 20210408026Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.Type: ApplicationFiled: September 7, 2021Publication date: December 30, 2021Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Miao SHEN, Li Hong XIAO, Yushi HU, Qian TAO, Mei Lan GUO, Yong ZHANG, Jian Hua SUN
-
Publication number: 20210296333Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.Type: ApplicationFiled: May 27, 2021Publication date: September 23, 2021Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Patent number: 11049866Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.Type: GrantFiled: January 17, 2020Date of Patent: June 29, 2021Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Publication number: 20210104531Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs, a channel structure extending vertically through the conductor/dielectric layer pairs in the memory stack, a TAC extending vertically through the conductor/dielectric layer pairs in the memory stack, and a dummy channel structure filled with a dielectric layer and extending vertically through the conductor/dielectric layer pairs in the memory stack.Type: ApplicationFiled: November 21, 2020Publication date: April 8, 2021Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Publication number: 20210082931Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Patent number: 10937806Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.Type: GrantFiled: May 5, 2020Date of Patent: March 2, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Qian Tao, Yushi Hu, Zhenyu Lu, Li Hong Xiao, Xiaowang Dai, Yu Ting Zhou, Zhao Hui Tang, Mei Lan Guo, ZhiWu Tang, Qinxiang Wei, Qianbing Xu, Sha Sha Liu, Jian Hua Sun, EnBo Wang
-
Patent number: 10879254Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.Type: GrantFiled: January 17, 2020Date of Patent: December 29, 2020Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Publication number: 20200266211Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Qian TAO, Yushi Hu, Zhenyu Lu, Li Hong Xiao, Xiaowang Dai, Yu Ting Zhou, Zhao Hui Tang, Mei Lan Guo, ZhiWu Tang, Qinxiang Wei, Qianbing Xu, Sha Sha Liu, Jian Hua Sun, EnBo Wang
-
Publication number: 20200161321Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.Type: ApplicationFiled: January 17, 2020Publication date: May 21, 2020Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Publication number: 20200161322Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.Type: ApplicationFiled: January 17, 2020Publication date: May 21, 2020Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Patent number: 10658378Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.Type: GrantFiled: July 27, 2018Date of Patent: May 19, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Qian Tao, Yushi Hu, Zhenyu Lu, Li Hong Xiao, Xiaowang Dai, Yu Ting Zhou, Zhao Hui Tang, Mei Lan Guo, ZhiWu Tang, Qinxiang Wei, Qianbing Xu, Sha Sha Liu, Jian Hua Sun, Enbo Wang
-
Publication number: 20200119031Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a first direction perpendicular to a substrate of the semiconductor device in a first region upon the substrate. The gate layers and the insulating layers are stacked of a stair-step form in a second region. The semiconductor device includes a channel structure that is disposed in the first region. The channel structure and the gate layers form a stack of transistors in a series configuration with the gate layers being gates for the transistors. The semiconductor device includes a contact structure disposed in the second region, and a first dummy channel structure disposed in the second region and around the contact structure. The first dummy channel structure is patterned with a first shape that is different from a second shape of the channel structure.Type: ApplicationFiled: March 28, 2019Publication date: April 16, 2020Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Miao Shen, Li Hong Xiao, Yushi Hu, Qian Tao, Mei Lan Guo, Yong Zhang, Jian Hua Sun
-
Publication number: 20200066739Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.Type: ApplicationFiled: October 1, 2018Publication date: February 27, 2020Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
-
Patent number: 10566336Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.Type: GrantFiled: October 1, 2018Date of Patent: February 18, 2020Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu