Patents by Inventor Mei-Lin Hsieh

Mei-Lin Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200395275
    Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung CHEN, Chih-Hung HSU, Mei-Lin HSIEH, Yi-Cheng HSU, Yuan-Chun CHEN, Yu-Shun HSIEH, Ko-Pu WU
  • Patent number: 8592962
    Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: November 26, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yu-Ying Lee, Mei-Lin Hsieh
  • Patent number: 8304865
    Abstract: A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: November 6, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yueh-Chen Hsu, Mei-Lin Hsieh, Chih-Hung Hsu, Kuang-Hsiung Chen, Yi-Cheng Hsu
  • Patent number: 8214139
    Abstract: Techniques are described for position source selection. In an implementation, an electronic device provides a variety of functionality including at least functionality to determine position. The electronic device may be further configured to select between a plurality of position sources to determine position based upon a variety of selection criteria. In an implementation, a last known position may be stored when position is being determined through the plurality of position sources. The last known position may be used as an alternative to determining position via the position sources when one or more of the position sources are unavailable. In another implementation, the last known position may be employed to automatically select one of the plurality of position sources to be used by the electronic device for determining position.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: July 3, 2012
    Assignee: Garmin Switzerland GmbH
    Inventors: Jason B. Yonker, Mei-Lin Hsieh, Bernhard P. Weisshaar, Haitao Huang, Merlin J. Smith
  • Publication number: 20120104584
    Abstract: A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.
    Type: Application
    Filed: August 29, 2011
    Publication date: May 3, 2012
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Hsiang-Ming Feng, Yu-Ying Lee, Mei-Lin Hsieh
  • Publication number: 20110062567
    Abstract: A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation.
    Type: Application
    Filed: August 19, 2010
    Publication date: March 17, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yueh-Chen Hsu, Mei-Lin Hsieh, Chih-Hung Hsu, Kuang-Hsiung Chen, Yi-Cheng Hsu
  • Publication number: 20090192709
    Abstract: Techniques are described for position source selection. In an implementation, an electronic device provides a variety of functionality including at least functionality to determine position. The electronic device may be further configured to select between a plurality of position sources to determine position based upon a variety of selection criteria. In an implementation, a last known position may be stored when position is being determined through the plurality of position sources. The last known position may be used as an alternative to determining position via the position sources when one or more of the position sources are unavailable. In another implementation, the last known position may be employed to automatically select one of the plurality of position sources to be used by the electronic device for determining position.
    Type: Application
    Filed: June 25, 2008
    Publication date: July 30, 2009
    Applicant: Garmin Ltd.
    Inventors: Jason B. Yonker, Mei-Lin Hsieh, Bernhard P. Weisshaar, Haitao Huang, Merlin J. Smith
  • Publication number: 20080230882
    Abstract: A chip package structure includes a die pad of which at least a notch is formed on at least one side and opposite to a mold gate. The die pad contributes to accelerating the injection of an encapsulating material, so as to exhaust the air in the mold in time, before the encapsulating material solidifies during the molding step, thereby overcoming or at least improving the problem of defects such as air bubbles in the encapsulation.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 25, 2008
    Inventors: Mei-Lin Hsieh, Chih-Hung Hsu, Kuang-Hsiung Chen
  • Publication number: 20080185698
    Abstract: A semiconductor package structure is disclosed. The structure comprises a die pad, a chip, leads, a recess, and an encapsulant. The chip is disposed on the die pad. The leads are disposed on a periphery of the die pad and electrically connected to the chip. The recess is formed on the top surface of at least one of the leads and extends to the outside surface thereof. The encapsulant is used for encapsulating the die pad, the chip, the leads, and the recess.
    Type: Application
    Filed: November 19, 2007
    Publication date: August 7, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yen-Wen Tseng, Mei-Lin Hsieh, Chih-Hung Hsu, Kuang-Hsiung Chen