Abstract: A method for diagnosing a root cause of failure using automated test equipment (ATE) is disclosed. The method comprises identifying a failing device under test (DUT). Further, the method comprises opening a test program log associated with the failing DUT and determining a time of failure by parsing through the test program log to find an identifier and timestamp associated with the failure. Finally, the method comprises displaying the test program log in a window within a graphical user interface, wherein a relevant section of the test program log associated with the failure is displayed in the window.

Abstract: A scalable test platform can include one or more of a plurality of different device interface boards and a plurality of primitives. The different device interface boards can be configured to provide a uniform interface to couple different types of DUTs and or DUTs with different form factors to the plurality of primitives. The plurality of primitives can be configured to distribute power to the DUTs, and to perform system level testing of the respective DUTs. The plurality of primitives can be configurable by a user to perform any number of system level tests on a number of different types of DUTs and or DUTs with different form factors.

Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a device interface board (DIB) configured to interface with a device under test (DUT); and a primitive configured to control the device interface board and testing of the device under test. The primitive is an independent self contained test control unit comprising: a backplane interface configured to couple with the device interface board; a power supply component configured to control power to the backplane interface; and a site module configured to control testing signals sent to the device interface board and device under test. The site module is reconfigurable for different test protocols. The primitive can be compatible with a distributed testing infrastructure. In one exemplary implementation, the primitive and device interface board are portable an operable to perform independent testing unfettered by other control components.

Abstract: Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a device interface board (DIB) configured to interface with a device under test (DUT); and a primitive configured to control the device interface board and testing of the device under test. The primitive is an independent self contained test control unit comprising: a backplane interface configured to couple with the device interface board; a power supply component configured to control power to the backplane interface; and a site module configured to control testing signals sent to the device interface board and device under test. The site module is reconfigurable for different test protocols. The primitive can be compatible with a distributed testing infrastructure. In one exemplary implementation, the primitive and device interface board are portable an operable to perform independent testing unfettered by other control components.

Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a primitive configured to control testing of a device under test (DUT) and a device interface board (DIB). The device interface board comprises: a loadboard, an environmental control component and a device under test access interface. The loadboard is configured to selectively couple with a device under test and a primitive. The environmental control component is configured to control environmental conditions. The device under test access interface is configured to allow robotic manipulation of the device under test. The manipulation can include selectively coupling the device under test to the loadboard. The device under test access interface can be configured to enable unobstructed access for robotic manipulation of the device under test.

Abstract: An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system comprises: a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by said controller processor, said plurality of programmable accelerator circuits for providing input test signals and for capturing output test signals; and a plurality of load boards respectively coupled to said plurality of programmable accelerator circuits, said plurality of load boards for applying said input test signals to a plurality of devices under test (DUTs) and for capturing said output test signals therefrom. In one exemplary implementation, each of said plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from said respective DUT; and sideband connectors. The sideband connectors receive test related information from said DUT.

Abstract: In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers.

Abstract: A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.

Abstract: In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers.

Abstract: A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.

Abstract: A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.

Abstract: A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.