Abstract: The invention relates to a program switch for mounting on a printed circuit board comprising a housing, an insulator component with contact elements arranged thereon, and a switching element for contacting the contact elements. The housing has at least two connection elements for connecting the program switch to adjacent program switches to form a program switch arrangement having an arbitrary number of poles. Production and stock keeping and sale of the program switch are simple.

Abstract: The invention relates to a program switch for mounting on a printed circuit board comprising a housing, an insulator component with contact elements arranged thereon, and a switching element for contacting the contact elements. The housing has at least two connection elements for connecting the program switch to adjacent program switches to form a program switch arrangement having an arbitrary number of poles. Production and stock keeping and sale of the program switch are simple.

Abstract: A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path.

Abstract: A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets.