Patents by Inventor Mei-Yen Li
Mei-Yen Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7386418Abstract: A yield analysis method. First, a wafer having multiple dies is inspected to obtain wafer defect data containing defect information for every die in the wafer. Then a wafer map and an overall yield are generated according to the wafer defect data. The wafer map displays defective dies and defect-free dies in the wafer. Then, first and second systematic limited yields are calculated in accordance with the wafer defect data and the wafer map, wherein the first systematic limited yield is calculated excluding defective dies with localized distribution, and the second systematic limited yield is calculated excluding defective dies with repeated distribution. Then a random defect limited yield is determined in accordance with the overall yield, the first systematic limited yield, and the second systematic limited yield.Type: GrantFiled: December 13, 2004Date of Patent: June 10, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Ting Lin, Chih-Hung Wu, Mei-Yen Li
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Patent number: 7205167Abstract: A method for detecting photoresist residue during semiconductor device manufacture includes developing photoresist on a surface of a semiconductor device to expose portions of the surface A plurality of etch paths are then partially etched into the surface and inspected to determine their depths.Type: GrantFiled: May 10, 2004Date of Patent: April 17, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: To-Yu Chen, Mei-Yen Li, Yung-Lung Hsu
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Publication number: 20060128039Abstract: A yield analysis method. First, a wafer having multiple dies is inspected to obtain wafer defect data containing defect information for every die in the wafer. Then a wafer map and an overall yield are generated according to the wafer defect data. The wafer map displays defective dies and defect-free dies in the wafer. Then, first and second systematic limited yields are calculated in accordance with the wafer defect data and the wafer map, wherein the first systematic limited yield is calculated excluding defective dies with localized distribution, and the second systematic limited yield is calculated excluding defective dies with repeated distribution. Then a random defect limited yield is determined in accordance with the overall yield, the first systematic limited yield, and the second systematic limited yield.Type: ApplicationFiled: December 13, 2004Publication date: June 15, 2006Inventors: Chen-Ting Lin, Chih-Hung Wu, Mei-Yen Li
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Publication number: 20050250227Abstract: A method for detecting photoresist residue during semiconductor device manufacture includes developing photoresist on a surface of a semiconductor device to expose portions of the surface A plurality of etch paths are then partially etched into the surface and inspected to determine their depths.Type: ApplicationFiled: May 10, 2004Publication date: November 10, 2005Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: To-Yu Chen, Mei-Yen Li, Yung-Lung Hsu
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Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing
Patent number: 6812156Abstract: A method of reducing particulate contamination in a deposition process including providing a semiconductor wafer having a process surface for depositing a deposition layer thereover according to one of a physical vapor deposition (PVD) and a chemical vapor deposition (CVD) process; depositing at least a portion of the deposition layer over the process surface; cleaning the semiconductor wafer including the process surface according to an ex-situ cleaning process to remove particulate contamination including at least one of spraying and scrubbing; and, repeating the steps of depositing and cleaning at least once to include reducing a level of occluded particulates.Type: GrantFiled: July 2, 2002Date of Patent: November 2, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Dyson Day, Mei-Yen Li, Ming-Te More, Hsing-Yuan Chu -
Patent number: 6716740Abstract: A method for depositing an inter-metal-dielectric layer on a semiconductor substrate by plasma chemical vapor deposition without the layer cracking defect is disclosed. The semiconductor substrate is first heat-treated in the same plasma process chamber to a temperature of at least 300° C. for a length of time sufficient to outgas a surface of the semiconductor substrate. The impurity gases absorbed on the surface of the semiconductor substrate can be effectively outgassed during the heat treatment process such that they are not trapped under an IMD layer deposited in a subsequent plasma deposition process. The method effectively minimizes or eliminates completely the IMD layer cracking defect of the dielectric layer.Type: GrantFiled: October 9, 2001Date of Patent: April 6, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Ming Wang, Long-Shang Chuang, Jui-Ping Chuang, Chin-Hsiung Ho, Mei-Yen Li, Chien-Kang Chou
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Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing
Publication number: 20040005787Abstract: A method of reducing particulate contamination in a deposition process including providing a semiconductor wafer having a process surface for depositing a deposition layer thereover according to one of a physical vapor deposition (PVD) and a chemical vapor deposition (CVD) process; depositing at least a portion of the deposition layer over the process surface; cleaning the semiconductor wafer including the process surface according to an ex-situ cleaning process to remove particulate contamination including at least one of spraying and scrubbing; and, repeating the steps of depositing and cleaning at least once to include reducing a level of occluded particulates.Type: ApplicationFiled: July 2, 2002Publication date: January 8, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Dyson Day, Mei-Yen Li, Ming-Te More, Hsing-Yuan Chu -
Publication number: 20030068902Abstract: A method for depositing an inter-metal-dielectric layer on a semiconductor substrate by plasma chemical vapor deposition without the layer cracking defect is disclosed. The semiconductor substrate is first heat-treated in the same plasma process chamber to a temperature of at least 300° C. for a length of time sufficient to outgas a surface of the semiconductor substrate. The impurity gases absorbed on the surface of the semiconductor substrate can be effectively outgassed during the heat treatment process such that they are not trapped under an IMD layer deposited in a subsequent plasma deposition process. The method effectively minimizes or eliminates completely the IMD layer cracking defect of the dielectric layer.Type: ApplicationFiled: October 9, 2001Publication date: April 10, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Ming Wang, Long-Shang Chuang, Jui-Ping Chuang, Chin-Hsiung Ho, Mei-Yen Li, Chien-Kang Chou
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Patent number: 6307628Abstract: End point detection during a CMP process on a semiconductor wafer employs confocal optics to increase signal-to-noise ratio near the end point. The use of confocal optics for sensing reflected light from the wafer surface exhibits greater selectivity where intermediate layers of metal are present in the wafer. A laser diode is used as a light source to examine the wafer surface. Light reflected back to the laser diode reduces its power state, and this power state is sensed by a current detector which outputs a signal representative of reflected light intensity.Type: GrantFiled: August 18, 2000Date of Patent: October 23, 2001Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Chun-Hung Lu, Mei-Yen Li
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Patent number: 6242355Abstract: A method for insulating metal conductors by spin-on-glass in inter-metal dielectric layers and devices formed by such method are disclosed. In the method, an additional step of scrubber clean is incorporated after an etch-back process on the spin-on-glass layer is conducted. Contaminating metal ions such as those of calcium is thus removed to eliminate formation of voids by such particles. The method can be easily implemented by including the additional scrubber clean step into a total wafer fabrication recipe.Type: GrantFiled: August 27, 1998Date of Patent: June 5, 2001Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Ding Dar Hu, Mei Yen Li, Li Dum Chen, Jing Kuan Lin
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Patent number: 6194249Abstract: The invention offers a solution to several problems associated wit IC packages that use a top layer of molded plastic. This has been achieved by inter-posing a dummy layer of dielectric material between the upper surface of the integrated circuit wafer and the molded plastic layer. This dummy layer is patterned and etched so that its surface becomes an alternating series of valleys and ridges, care being taken to ensure that all wiring lines are protected by being within ridges. This structure serves both to protect the wiring lines during the application of the molded plastic and, because of the large surface area of contact between plastic and wafer, excellent adhesion of the molded plastic to the wafer is obtained.Type: GrantFiled: November 1, 1999Date of Patent: February 27, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Ming Hsien Chen, Mei-Yen Li, Li-Don Chen, Chih-Ming Chen
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Patent number: 6087217Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge capacity and a DRAM capacitor formed by such method. The method can be carried out by first depositing an oxide layer on a lower polysilicon electrode layer on a semiconductor structure, then polishing the top surface of the oxide layer to form an uneven surface which provides increased surface area, and then anisotropically etching away the oxide layer while reproducing the uneven surface of the oxide layer onto the lower polysilicon electrode layer such that an increased charge capacity can be realized. The anisotropic etch chemistry should be selected such that the etchant etches away both the oxide layer and the polysilicon layer, and preferably, the etchant should have a higher selectivity toward polysilicon and a lower selectivity toward oxide such that the oxide layer can be completely removed while only a portion of the polysilicon layer is removed to form the uneven surface.Type: GrantFiled: November 5, 1997Date of Patent: July 11, 2000Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mei-Yen Li, L. C. Chen
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Patent number: 6033967Abstract: The present invention discloses a method for increasing capacitance in DRAM capacitors by the operating steps of first providing a cavity in a semiconductor substrate, then depositing a first polysilicon layer in the cavity, and a metal layer on top of the polysilicon layer to form a silicide layer. The semiconductor substrate is then heat treated in a rapid thermal processing method so that the metal silicide layer forms an island structure on top of the first polysilicon layer. The first polysilicon layer can then be isotropically etched by using the metal silicide island structure as a mask to form an island structure in the first polysilicon layer. Additional dielectric layer and polysilicon layers are then deposited to form the insulating layer and the upper electrode for the capacitor. The increased surface area, i.e., approximately two times, of the lower electrode polysilicon layer greatly increases its storage area for the capacitor and therefore greatly improves its capacitance.Type: GrantFiled: July 21, 1997Date of Patent: March 7, 2000Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mei-Yen Li, L. C. Chen
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Patent number: 6020234Abstract: A method is disclosed for increasing the capacitance of high-density DRAM devices by microlithographic patterning. A semiconductor substrate having a MOS transistor comprising a gate and source/drain regions, and a word line and a bit line is provided. A layer of inter-poly oxide is deposited over the substrate and planarized. Contact holes are etched in the oxide layer until the substrate is exposed. A layer of photoresist is next blanket deposited over the substrate. Using microlithographic methods, the photoresist is then patterned with in-line or staggered micron size features and the underlying inter-poly oxide layer is etched using the photoresist as a mask. The resulting inter-poly oxide surface, therefore, acquires the shape of a micro-folded topography having a roughened surface area of many folds larger than the original flat surface.Type: GrantFiled: March 5, 1998Date of Patent: February 1, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Mei-Yen Li, Ding-Dar Hu, Li-chun Chen