Patents by Inventor Mei-Chen Chen

Mei-Chen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9653404
    Abstract: The present invention provides an overlay target. The overlay target includes a plurality of first pattern blocks and a plurality of second pattern blocks. The first pattern blocks and the second patterns blocks are arranged in array by being separated by at least one first gaps stretching along a first direction and at least one second gaps stretching along a second direction. Each first pattern block is composed of a plurality of first stripe patterns stretching along a third direction, and each second pattern block is composed of a plurality of second stripe patterns stretching along a fourth direction. The first direction is orthogonal to the second direction, the third direction and the fourth direction are 45 degrees relative to the first direction.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Jing Wang, En-Chiuan Liou, Mei-Chen Chen, Han-Lin Zeng, Chia-Hung Lin, Chun-Chi Yu
  • Patent number: 9530646
    Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, An-Chi Liu, Chih-Wei Wu, Jyh-Shyang Jenq, Shih-Fang Hong, En-Chiuan Liou, Ssu-I Fu, Yu-Hsiang Hung, Chih-Kai Hsu, Mei-Chen Chen, Chia-Hsun Tseng
  • Publication number: 20160247678
    Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.
    Type: Application
    Filed: February 24, 2015
    Publication date: August 25, 2016
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, An-Chi Liu, Chih-Wei Wu, Jyh-Shyang Jenq, Shih-Fang Hong, En-Chiuan Liou, Ssu-I Fu, Yu-Hsiang Hung, Chih-Kai Hsu, Mei-Chen Chen, Chia-Hsun Tseng
  • Patent number: 9373505
    Abstract: In this disclosure, a mark segmentation method and a method for manufacturing a semiconductor structure applying the same are provided. The mark segmentation method comprises the following steps. First, a plurality of segments having a width WS and separated from each other by a space SS formed on a substrate are identified by a processor. Thereafter, a plurality of marks are set over the segments by the processor. This step comprises: (1) adjusting a width WM of each one of the marks being equal to m(WS+SS)+WS or m(WS+SS)+SS by the processor, wherein m is an integer; and (2) adjusting a space SM of adjacent two of the marks by the processor such that WM+SM=n(WS+SS), wherein n is an integer.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: June 21, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Ying Huang, Jen-Hsiu Li, Mei-Chen Chen, Ya-Ling Chen, Yi-Jing Wang, Chi-Ming Huang
  • Publication number: 20150294058
    Abstract: In this disclosure, a mark segmentation method and a method for manufacturing a semiconductor structure applying the same are provided. The mark segmentation method comprises the following steps. First, a plurality of segments having a width WS and separated from each other by a space SS formed on a substrate are identified by a processor. Thereafter, a plurality of marks are set over the segments by the processor. This step comprises: (1) adjusting a width WM of each one of the marks being equal to m(WS+SS)+WS or m(WS+SS)+SS by the processor, wherein m is an integer; and (2) adjusting a space SM of adjacent two of the marks by the processor such that WM+SM=n(WS+SS), wherein n is an integer.
    Type: Application
    Filed: May 15, 2014
    Publication date: October 15, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Ying Huang, Jen-Hsiu Li, Mei-Chen Chen, Ya-Ling Chen, Yi-Jing Wang, Chi-Ming Huang