Abstract: The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

Abstract: A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the <100> direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.

Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

Abstract: The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer.

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

Abstract: A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.

Abstract: The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer.

Abstract: The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer.

Abstract: A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.

Abstract: NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

Abstract: The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

Abstract: An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction. The <110> direction is perpendicular to the <100> direction. A method of fabricating such as integrated semiconductor structure is also provided.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer.