Patents by Inventor Meir Hasko

Meir Hasko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9083348
    Abstract: Aspects of the disclosure provide a method for tuning delay. The method includes driving, during a calibration stage, at least one test signal from an integrated circuit onto a plurality of outside transmission lines that are coupled to the integrated circuit, measuring a timing of the at least one test signal transmitted and reflected over the plurality of outside transmission lines, and selectively delaying, using units disposed within the integrated circuit, signals subsequently transmitted over the plurality of outside transmission lines based on the timing of the at least one test signal, in order to align transmission times of the subsequently transmitted signals.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: July 14, 2015
    Assignee: Marvel Israel (M.I.S.L) Ltd.
    Inventors: Dan Azeroual, Meir Hasko
  • Patent number: 8972755
    Abstract: An integrated circuit includes an operational circuit module receiving a supply voltage from a voltage regulator external to the integrated circuit, and an adaptive voltage scaling module to adjust the supply voltage based on performance characteristics of the operational circuit module. The adaptive voltage scaling module can include a performance monitoring module disposed on the integrated circuit and configured to generate at least an indicator corresponding to at least one performance characteristic of the operational circuit module. The adaptive scaling module can include a voltage requirement determination and voltage feedback generator module disposed on the integrated circuit and coupled to the performance monitoring module. The voltage requirement determination and voltage feedback generator module is configured to output a feedback voltage signal having a voltage level as a function of at least the indicator.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 3, 2015
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Meir Hasko, Erez Reches, Reuven Ecker, Ido Bourstein
  • Patent number: 8615669
    Abstract: An integrated circuit includes an operational circuit module receiving a supply voltage from a voltage regulator external to the integrated circuit, and an adaptive voltage scaling module to adjust the supply voltage based on performance characteristics of the operational circuit module. The adaptive voltage scaling module can include a performance monitoring module disposed on the integrated circuit and configured to generate at least an indicator corresponding to at least one performance characteristic of the operational circuit module. The adaptive scaling module can include a voltage requirement determination and voltage feedback generator module disposed on the integrated circuit and coupled to the performance monitoring module. The voltage requirement determination and voltage feedback generator module is configured to output a feedback voltage signal having a voltage level as a function of at least the indicator.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 24, 2013
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Meir Hasko, Erez Reches, Reuven Ecker, Ido Bourstein
  • Patent number: 8370654
    Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first operational circuit module receiving a first supply voltage from a first voltage regulator that is external to the integrated circuit, and a first adaptive voltage scaling module to adjust the first supply voltage based on performance characteristics of the first operational circuit module. In an embodiment of the disclosure, the first adaptive voltage scaling module includes a first performance monitoring module. The performance monitoring module is disposed on the integrated circuit, and is configured to generate at least a first indicator corresponding to at least one performance characteristic of the first operational circuit module. Further, the first adaptive scaling module includes a first voltage requirement determination and voltage feedback generator module that is disposed on the integrated circuit, and is coupled to the first performance monitoring module.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: February 5, 2013
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Meir Hasko, Erez Reches, Reuven Ecker, Ido Bourstein
  • Patent number: 8164348
    Abstract: Aspects of the disclosure can provide an integrated circuit (IC) chip. The IC chip may adjust delays at its interface to compensate for outside transmission line delays. The interface of the IC chip can include a plurality of input/output (IO) modules coupled to a plurality of outside transmission lines, respectively. Each of the IO module can further include at least one variable delay element configured to delay transmission over the corresponding outside transmission line based on an actually measured transmission delay of the outside transmission line, in order to align signals transmitted by the plurality of outside transmission lines in a desired manner.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: April 24, 2012
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Dan Azeroual, Meir Hasko
  • Patent number: 7838778
    Abstract: A circuit board having a method therefor comprises a first circuit board layer comprising a first surface having disposed thereon a first plurality of lands arranged in three rows and comprising at least one group of the lands, wherein each group of the lands comprises first and second ones of the lands arranged in a first one of the rows, third, fourth, and fifth ones of the lands arranged in a second one of the rows, and sixth and seventh ones of the lands arranged in a third one of the rows, wherein the second one of the rows is adjacent to, and lies between, the first one of the rows and the third one of the rows; and respective traces extending from the first, second, third, fourth, fifth, and sixth ones of the lands between the sixth and seventh ones of the lands.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: November 23, 2010
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Meir Hasko, Dan Azeroual