Abstract: Three metal layer customizable gate array devices and techniques to customize them are disclosed. Such a device incorporates an integrated circuit blank having a plurality of transistors and at least three metal layers. A plurality of fusible links interconnects said plurality of transistors into an inoperable circuit. A laser ablative etch resistant coating is formed over the device. Later, the coating is ablated by laser at locations overlaying designated fuse locations. The device is then etched for selectably removing some of the fusible links, thereby converting the inoperable integrated circuit blank into an operable gate array device.

Abstract: Customizable semiconductor devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.

Abstract: A personalizable multi-chip carrier including a substrate, first and second pluralities of conductors arranged on respective first and second parallel planes, the first and second pluralities of conductors defining a grid of conductors arranged over the substrate and defining a multiplicity of crossing locations at which conductors of the first and second pluralities cross each other, apparatus for interconnecting the first and second pluralities of conductors at locations adjacent the multiplicity of crossing locations and including a plurality of fusible links.

Abstract: An active matrix of a display panel having a plurality of array elements and at least two data busses, each array element including a primary switch initially connected to the data busses and at least one connectable secondary switch, wherein, when the primary switch is disconnected from the busses, one of the at least one secondary switches is connected to the busses.

Abstract: A programmable integrated circuit for prototyping applications including a first patterned metal layer, an insulation layer formed over the first metal layer and a second patterned metal layer formed over the insulation layer, the first and second patterned metal layers being formed with selectably removable regions, the insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions a coating comprising a layer of a dielectric material of high laser radiation absorption coefficient.

Abstract: An integrated circuit which is readily customized by the user to his specific requirements and is thus suitable for prototype and small scale production.

Abstract: A technique for providing a radiation formable conductive link in an integrated circuit comprising the steps of: depositing a plurality of aluminum conductors on an exposed surface of an otherwise completed integrated circuit, and forming a bridge of amorphous silicon layer joining the aluminum conductors at selected locations, whereby subsequent laser radiation produces diffusion of aluminum into the amorphous silicon, producing a highly conductive aluminum doped silicon bridge.

Abstract: A selectably customizable semiconductor device first and second metal layers disposed in respective first and second planes and including respective first and second elongate strips, conductive branches being provided in association with the elongate strips.

Abstract: A technique for production of customized integrated circuits comprising the steps of providing an integrated circuit blank having at least first and second metal layers including portions arranged for selectable removal to provide desired customization of said integrated circuit blank, and thereafter etching at least said first metal layer to customize said integrated circuit blank.