Abstract: In order to enable asynchronous, autonomous reception beam switching at a UE while minimizing degradation due to a transient in link performance, a method, apparatus, and computer-readable medium for wireless communication are provided. The apparatus receives CSI-RS on different reception beams in different symbols, wherein one reception beam being a current serving reception beam, and determines whether to switch to a different reception beam based on a SPEFF metric for the different reception beam and/or a severity of a potential link transient qualified in terms of the expected CQI/MCS degradation in the channel. The apparatus may switch from a current serving reception beam to a second reception beam when a first channel quality for the current serving reception beam is within a threshold value of a second channel quality for the second reception beam, the second channel quality being measured using a current configuration.

Abstract: In order to enable asynchronous, autonomous reception beam switching at a UE while minimizing degradation due to a transient in link performance, a method, apparatus, and computer-readable medium for wireless communication are provided. The apparatus receives CSI-RS on different reception beams in different symbols, wherein one reception beam being a current serving reception beam, and determines whether to switch to a different reception beam based on a SPEFF metric for the different reception beam and/or a severity of a potential link transient qualified in terms of the expected CQI/MCS degradation in the channel. The apparatus may switch from a current serving reception beam to a second reception beam when a first channel quality for the current serving reception beam is within a threshold value of a second channel quality for the second reception beam, the second channel quality being measured using a current configuration.

Abstract: In order to enable asynchronous, autonomous reception beam switching at a UE while minimizing degradation due to a transient in link performance, a method, apparatus, and computer-readable medium for wireless communication are provided. The apparatus receives CSI-RS on different reception beams in different symbols, wherein one reception beam being a current serving reception beam, and determines whether to switch to a different reception beam based on a SPEFF metric for the different reception beam and/or a severity of a potential link transient qualified in terms of the expected CQI/MCS degradation in the channel. The apparatus may switch from a current serving reception beam to a second reception beam when a first channel quality for the current serving reception beam is within a threshold value of a second channel quality for the second reception beam, the second channel quality being measured using a current configuration.

Abstract: In order to enable asynchronous, autonomous reception beam switching at a UE while minimizing degradation due to a transient in link performance, a method, apparatus, and computer-readable medium for wireless communication are provided. The apparatus receives CSI-RS on different reception beams in different symbols, wherein one reception beam being a current serving reception beam, and determines whether to switch to a different reception beam based on a SPEFF metric for the different reception beam and/or a severity of a potential link transient qualified in terms of the expected CQI/MCS degradation in the channel. The apparatus may switch from a current serving reception beam to a second reception beam when a first channel quality for the current serving reception beam is within a threshold value of a second channel quality for the second reception beam, the second channel quality being measured using a current configuration.

Abstract: Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system.

Abstract: Inter-processor communication (IPC) apparatus and a method for providing communication between two processors having a shared memory, the IPC apparatus including an arbitrated bus coupling the processors to one another and to the memory, a buffer in the shared memory associated with each processor, and at least one pair of First In First Out hardware units (FIFOs) coupled to each processor, the FIFOs holding pointers to addresses in the buffer associated with that processor, wherein a first of the pair of FIFOs (an empty buffer FIFO) is configured to hold pointers to empty portions of the buffer while the second of the pair of FIFOs (a message FIFO) is configured to hold pointers to portions of the buffer having data therein.

Abstract: An algebraic processor as part of a wireless telecommunication system, including pre-computed Look Up Tables (LUT), used for computing a number of different functions using linear interpolation. Preferably, the step of computing is implemented in a multiplier-accumulator having a SIMD structure.

Abstract: Inter-processor communication (IPC) apparatus and a method for providing communication between two processors having a shared memory, the IPC apparatus including an arbitrated bus coupling the processors to one another and to the memory, a buffer in the shared memory associated with each processor, and at least one pair of First In First Out hardware units (FIFOs) coupled to each processor, the FIFOs holding pointers to addresses in the buffer associated with that processor, wherein a first of the pair of FIFOs (an empty buffer FIFO) is configured to hold pointers to empty portions of the buffer while the second of the pair of FIFOs (a message FIFO) is configured to hold pointers to portions of the buffer having data therein.

Abstract: A method and system for processing LLRs, in a receiver, of transmissions over a wireless telecommunication system, the method including receiving multiple soft symbols, selecting a set of appropriate instructions for LLR calculation for the soft symbols, arranging the soft symbols in a register of a processor according to the selected instructions, selecting an appropriate single instruction from the set of instructions to be implemented by the processor using the soft symbols in the register as operands, and calculating, by a computation unit, multiple LLR values for the multiple soft symbols, in parallel, by means of the selected instruction.

Abstract: A method and system for processing LLRs, in a receiver, of transmissions over a wireless telecommunication system, the method including receiving multiple soft symbols, selecting a set of appropriate instructions for LLR calculation for the soft symbols, arranging the soft symbols in a register of a processor according to the selected instructions, selecting an appropriate single instruction from the set of instructions to be implemented by the processor using the soft symbols in the register as operands, and calculating, by a computation unit, multiple LLR values for the multiple soft symbols, in parallel, by means of the selected instruction.

Abstract: Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system.

Abstract: A receiver for wireless broadband telecommunication transmissions, the receiver including a demodulator for receiving transmitted modulated symbols, a channel deinterleaver memory coupled to the demodulator for receiving interleaved soft symbols and outputting deinterleaved soft symbols, an LLR calculator coupled to the channel deinterleaver memory for receiving the deinterleaved soft symbols and calculating LLRs therefore, a descrambler coupled to the LLR calculator for descrambling the LLRs, and an interleaved scrambling sequence generator coupled to the descrambler for generating an interleaved scrambling sequence and providing it to the descrambler.

Abstract: An embodiment of the present invention is a technique to simulate performance of a multi-core system. A micro-architecture effect is estimated from each core in the multi-core system. A model of a memory hierarchy associated with each core is simulated. The simulated model of the memory hierarchy is superpositioned on the estimated micro-architecture effect to produce a performance figure for the multi-core system.

Abstract: Devices, systems and methods of accessing a memory. For example, an apparatus includes: at least one buffer to store a data line read from a memory; and gatherer to store at least a portion of said data line and at least a portion of a previously read data line stored in said at least one buffer.

Abstract: An embodiment of the present invention is a technique to simulate performance of a multi-core system. A micro-architecture effect is estimated from each core in the multi-core system. A model of a memory hierarchy associated with each core is simulated. The simulated model of the memory hierarchy is superpositioned on the estimated micro-architecture effect to produce a performance figure for the multi-core system.

Abstract: According to some embodiments, time information is associated with data received at a digital signal processor based physical layer processing unit.

Abstract: A shared memory access controller method and system utilize a load monitor unit able to monitor memory access requirements of one or more devices coupled to a memory. A load manager unit coupled to the load monitor unit is able to set an access policy for at least one of the devices in relation to data from the load monitor. There is also an access control unit connected to the load manager unit and able to provide a device access to the memory based on the device's associated access policy.

Abstract: The central processing unit of an integrated circuit data processing system includes both means for processing a first non-maskable interrupt (NMI) request received by the data processing system on a first NMI request line and means for processing a second NMI request received by the data processing system on a second NMI request line different from the first NMI request line and within a predefined time period after receipt of the first NMI request. Both. NMI requests are serviced by the data processing system even if the second NMI request is received prior to completion of processing of the first request.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.

Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.