Patents by Inventor Meiram Heller

Meiram Heller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuits and methods for selectively latching the output of an adder
    Patent number: 6731138
    Abstract: Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The outputs of the NAND gates are coupled to a multiplexer. A set dominant latch is coupled to the clock signal and an output of the multiplexer.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: May 4, 2004
    Assignee: Intel Corporatioin
    Inventors: Meiram Heller, Eitan Emanuel Rosen
  • Circuits and methods for selectively latching the output of an adder
    Publication number: 20040021482
    Abstract: Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The outputs of the NAND gates are coupled to a multiplexer. A set dominant latch is coupled to the clock signal and an output of the multiplexer.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 5, 2004
    Inventors: Meiram Heller, Eitan Emanuel Rosen