Abstract: A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.

Abstract: A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instructions execute in a statically determinable way. At least two processing blocks process instructions from the stream of instructions. A first processing block has a set of physical registers associated with it for storing data values being processed by the first processing block. Renaming circuitry associated with the first processing block maps architectural registers specified in instructions to be processed by the first processing block to physical registers within the set of physical registers. A second processing block has a set of physical registers associated with it for storing data values being processed by the second processing block. The second processing block and registers do not support renaming.

Abstract: A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster.

Abstract: A data processing apparatus operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may cause a break in an instruction flow and non-exception instructions being instructions that execute in a statically determinable way, said data processing apparatus comprising: at least two processing blocks for processing instructions from said stream of instructions; a first processing block having a set of physical registers associated with it for storing data values being processed by said first processing block, renaming circuitry associated with said first processing block for mapping architectural registers specified in instructions to be processed by said first processing block to physical registers within said set of physical registers; a second processing block having a set of physical registers associated with it for storing data values being processed by said second

Abstract: The present application discloses register renaming circuitry for mapping registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers being registers specified by instructions within an instruction set and said physical set of registers being registers within a processor for processing instructions of said instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said register renaming circuitry comprising: a first data store for storing a future renaming table, said future renaming table comprising renaming values for mapping registers from said architectural set of registers to registers in said physical set of registers for instructions that are to be executed or are currently being executed by said processor; a second da

Abstract: A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster.

Abstract: A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.