Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. Also disclosed is a method and apparatus for speeding conversion of a number in binary format to decimal format by first stripping leading zeroes before the highest order non-zero bit of the binary number, and only allocating enough memory storage bits to hold the resultant decimal number. A multiplexer is used to apply a partial sum during conversion concurrently to both inputs of an adder for doubling.

Abstract: Processor apparatus is described for performing binary and decimal arithmetic operations. In performing decimal multiplication with the processor apparatus, to reduce the amount of processing to be done with the apparatus and thereby speed up the performance of the decimal multiplication, the leading zeroes prefixing the highest order significant digit in both a multiplier and a multiplicand are identified, counted and removed. Decimal multiplication is then performed using the stripped multiplier and multiplicand, and to the resultant partial product a number of zeroes are prefixed equal to the number of zeroes originally stripped from the multiplier and multiplicand. The result is the product of the original multiplier and multiplicand.

Abstract: What is disclosed is apparatus making up an arithmetic logic unit and utilizing a programmable read-only memory (PROM) to perform arithmetic functions for an associated processor. The PROM is used as a look-up table for computation results. Operands used to perform a mathematical computation make up an address to the PROM which is used to read out the computation result stored therein. Also stored in the PROM as part of each computation result are information bits indicating if the computation result is a valid answer. These bits are also read out and stored in flip-flops to indicate to the processor if the computation result is valid or invalid.

Abstract: Apparatus is provided for addressing a memory by word and by one of a number of nibbles within a word, with the ability to increment or decrement nibble and word addresses and thereby access adjacent nibbles and words without having to generate new nibble and word addresses. An initial word address is placed in an address counter and an initial nibble address is placed in a nibble control. The two addresses indicate a particular nibble within a particular word. Thereafter, only increment or decrement signals are provided to increment and decrement the nibble address and/or the word address. A nibble counter counts the increment and decrement nibble signals and when the last or first nibble in a word is addressed, an increment or decrement word address signal is respectively generated that changes the word address stored in the address counter.