Patents by Inventor Melinda J. Brown
Melinda J. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9858077Abstract: Issuing instructions to execution pipelines based on register-associated preferences and related instruction processing circuits, systems, methods, and computer-readable media are disclosed. In one embodiment, an instruction is detected in an instruction stream. Upon determining that the instruction specifies at least one source register, an execution pipeline preference(s) is determined based on at least one pipeline indicator associated with the at least one source register in a pipeline issuance table, and the instruction is issued to an execution pipeline based on the execution pipeline preference(s). Upon a determination that the instruction specifies at least one target register, at least one pipeline indicator associated with the at least one target register in the pipeline issuance table is updated based on the execution pipeline to which the instruction is issued. In this manner, optimal forwarding of instructions may be facilitated, thus improving processor performance.Type: GrantFiled: January 15, 2013Date of Patent: January 2, 2018Assignee: QUALCOMM IncorporatedInventors: Melinda J. Brown, James N. Dieffenderfer, Michael W. Morrow, Brian M. Stempel, Michael S. McIlvaine
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Patent number: 9477476Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register.Type: GrantFiled: November 27, 2012Date of Patent: October 25, 2016Assignee: QUALCOMM IncorporatedInventors: Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Brian Michael Stempel, Michael Scott McIlvaine, Rodney Wayne Smith, Jeffrey M. Schottmiller, Andrew S. Irwin
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Patent number: 9411590Abstract: An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.Type: GrantFiled: March 15, 2013Date of Patent: August 9, 2016Assignee: QUALCOMM IncorporatedInventors: Rodney Wayne Smith, Jeffery M. Schottmiller, Michael Scott McIlvaine, Brian Michael Stempel, Melinda J. Brown, Daren Eugene Streett
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Patent number: 9195466Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.Type: GrantFiled: November 14, 2012Date of Patent: November 24, 2015Assignee: QUALCOMM IncorporatedInventors: Melinda J. Brown, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel, Rodney Wayne Smith, Jeffery M. Schottmiller, Andrew S. Irwin, Michael William Morrow
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Patent number: 9146741Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. In this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.Type: GrantFiled: October 19, 2012Date of Patent: September 29, 2015Assignee: QUALCOMM IncorporatedInventors: Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Brian Michael Stempel, Michael Scott McIlvaine
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Publication number: 20140281394Abstract: An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Rodney Wayne Smith, Jeffery M. Schottmiller, Michael Scott McIlvaine, Brian Michael Stempel, Melinda J. Brown, Daren Eugene Streett
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Publication number: 20140281429Abstract: Embodiments disclosed herein include eliminating redundant synchronization barriers from execution pipelines in instruction processing circuits. Related processor systems, methods, and computer-readable media are also disclosed. By tracking the occurrence of synchronization events, unnecessary software synchronization operations may be identified and eliminated, thus improving performance of a central processing unit (CPU). In one embodiment, a method for eliminating redundant synchronization barriers in an instruction stream is provided. The method comprises determining whether a next instruction comprises a synchronization barrier of a type corresponding to a first synchronization event. The method also comprises eliminating the next instruction from the instruction stream, responsive to determining that the next instruction comprises a synchronization barrier of a type corresponding to the first synchronization event.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Melinda J. Brown, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel, Daren Eugene Streett
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Publication number: 20140149722Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register.Type: ApplicationFiled: November 27, 2012Publication date: May 29, 2014Applicant: QUALCOMM INCORPORATEDInventors: Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Brian Michael Stempel, Michael Scott McIlvaine, Rodney Wayne Smith, Jeffrey M. Schottmiller, Andrew S. Irwin
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Publication number: 20140047221Abstract: Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also detects a flag-consuming instruction in the instruction stream indicating a second operation consuming the first flag result as an input. The instruction processing circuit generates a fused instruction indicating the first operation generating the first flag result and indicating the second operation consuming the first flag result as the input. In this manner, as a non-limiting example, the fused instruction eliminates a potential for a read-after-write hazard between the flag-producing instruction and the flag-consuming instruction.Type: ApplicationFiled: March 7, 2013Publication date: February 13, 2014Applicant: QUALCOMM INCORPORATEDInventors: Andrew S. Irwin, James Norris Dieffenderfer, Melinda J. Brown, Jeffery M. Schottmiller, Brian Michael Stempel, Michael Scott McIlvaine, Rodney Wayne Smith, Michael William Morrow
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Publication number: 20130326197Abstract: Issuing instructions to execution pipelines based on register-associated preferences and related instruction processing circuits, systems, methods, and computer-readable media are disclosed. In one embodiment, an instruction is detected in an instruction stream. Upon determining that the instruction specifies at least one source register, an execution pipeline preference(s) is determined based on at least one pipeline indicator associated with the at least one source register in a pipeline issuance table, and the instruction is issued to an execution pipeline based on the execution pipeline preference(s). Upon a determination that the instruction specifies at least one target register, at least one pipeline indicator associated with the at least one target register in the pipeline issuance table is updated based on the execution pipeline to which the instruction is issued. In this manner, optimal forwarding of instructions may be facilitated, thus improving processor performance.Type: ApplicationFiled: January 15, 2013Publication date: December 5, 2013Applicant: QUALCOMM IncorporatedInventors: Melinda J. Brown, James N. Dieffenderfer, Michael W. Morrow, Brian M. Stempel, Michael S. Mcllvaine
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Publication number: 20130326195Abstract: Preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media are disclosed. In this regard, a method for processing instructions in a central processing unit (CPU) is provided. The method comprises decoding an instruction comprising a plurality of bits, and generating a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. If the parity error indicator indicates that the parity error exists in the plurality of bits, one or more of the plurality of bits are modified to indicate a no execution operation (NOP), without effecting a roll back of a program counter of the CPU and without re-decoding the instruction. In this manner, the possibility of the parity error causing an inadvertent execution of an unpredictable instruction is reduced.Type: ApplicationFiled: March 7, 2013Publication date: December 5, 2013Applicant: QUALCOMM INCORPORATEDInventors: Michael Scott McIlvaine, James Norris Dieffenderfer, Brian Michael Stempel, Leslie Mark DeBruyne, Melinda J. Brown
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Publication number: 20130311754Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.Type: ApplicationFiled: November 14, 2012Publication date: November 21, 2013Applicant: QUALCOMM INCORPORATEDInventors: Melinda J. Brown, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel, Rodney Wayne Smith, Jeffrey M. Schottmiller, Andrew S. Irwin, Michael William Morrow
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Publication number: 20130290683Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. in this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.Type: ApplicationFiled: October 19, 2012Publication date: October 31, 2013Applicant: QUALCOMM INCORPORATEDInventors: Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Brian Michael Stempel, Michael Scott McIlvaine