Patents by Inventor Melissa E. Grupen-Shemansky

Melissa E. Grupen-Shemansky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6482289
    Abstract: An assembly and method for connecting two substrates utilizes a nonconductive laminant that is compatible when wet with a conductive paste when wet. Thus, the curing of the nonconductive laminant and the conductive paste may be performed together. The nonconductive laminant also cures in a shorter time than those previously available, thus the stress on the semiconductor device created by exposure to the cure temperature is additionally reduced.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: November 19, 2002
    Assignee: Motorola, Inc.
    Inventors: Treliant Fang, Melissa E. Grupen-Shemansky, Shun-Meen Kuo
  • Patent number: 6022761
    Abstract: A method for connecting substrates includes using an adhesive interposer structure (11) to bond a semiconductor device (26) to a substrate (18). The adhesive interposer structure (11) includes a non-conductive adhesive laminant (12) and conductive adhesive bumps (13). The conductive adhesive bumps (13) provide a conductive path between conductive bumps (27) on the semiconductor device (26) and conductive metal pads (21) located on the substrate (18). In an alternative embodiment, a conductive adhesive material (34) is screen or stencil printed into vias (39) located on a printed circuit board (38) to form conductive adhesive bumps (33). A non-conductive adhesive (52) is then screen or stencil printed onto the printed circuit board (38) adjacent the conductive adhesive bumps (33). A semiconductor die is then connected to the structure.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: February 8, 2000
    Assignee: Motorola, Inc.
    Inventors: Melissa E. Grupen-Shemansky, Jong-Kai Lin, Theodore G. Tessier
  • Patent number: 5346848
    Abstract: A silicon wafer and a III-V semiconductor wafer are bonded together through a bonding interlayer which is deposited on the III-V semiconductor wafer. By forming the bonding interlayer on the III-V semiconductor wafer, rather than the silicon wafer, the bonding process is facilitated, creating a sufficiently strong bond to carry out further processing. The III-V semiconductor wafer is thinned to relieve stress after the bonding procedure. The bonded wafers may be subjected to a second bonding procedure to increase the bond strength. The bonded wafers can then be subjected to high temperature processing used in semiconductor device fabrication.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: September 13, 1994
    Assignee: Motorola, Inc.
    Inventors: Melissa E. Grupen-Shemansky, Bertrand F. Cambou
  • Patent number: 5268065
    Abstract: A method for thinning a semiconductor wafer (11) is provided. An support film (15) is mounted to the semiconductor wafer (11). The support film (15) provides support for a semiconductor wafer during thinning as well as protection for a front-side (12) of the semiconductor wafer (11). After mounting the support film (15) to the semiconductor wafer (11), a back-side (13) of the semiconductor wafer is etched in a two step process. First the back-side (13) undergoes a mechanical grinding followed by a chemical etch. A metal film (18) may be sputtered on the back-side (13). The semiconductor wafer (11) having the support film (15) is placed in a tape frame (20) for dicing operations and the support film (15) is removed from the front-side (12) of the semiconductor wafer (11).
    Type: Grant
    Filed: December 21, 1992
    Date of Patent: December 7, 1993
    Assignee: Motorola, Inc.
    Inventor: Melissa E. Grupen-Shemansky
  • Patent number: 5080933
    Abstract: A method for selectively depositing polysilicon on a semiconductor surface (13) is accomplished by preparing the surface (13) in a manner to provide a contamination free surface. The contamination free semiconductor surface is placed into a chemical vapor deposition reactor. The semiconductor surface (13) is exposed to a single crystal inhibitor gas to prevent formation of single crystal silicon on surface (13). Semiconductor surface (13) is then exposed to a silicon containing gas with a hydrogen source to form the polysilicon.
    Type: Grant
    Filed: September 4, 1990
    Date of Patent: January 14, 1992
    Assignee: Motorola, Inc.
    Inventors: Melissa E. Grupen-Shemansky, Hang M. Liaw