Abstract: A processor includes an execution unit for executing a message padding instruction including an operand field indicating a register buffering a message block segment of a message block to be padded and a mode field indicating which hash functions is to be applied to the message block. The execution unit includes a padding circuit configured to receive a message block segment from a register indicated by the operand field, where the message block spans multiple registers in a register file. Based on which hash function is indicated by the mode field, the padding circuit selects a byte location in the message block segment at which to insert at least one padding byte and inserts the at least one padding byte at the byte location within the message block segment. The message block segment as padded by the at least one padding byte is written back to the register file.

Abstract: Function approximation includes receiving a number value to be input to a function. The number value includes a first and second plurality of bits. A first approximation value of a function is determined using the first plurality of bits as an index to a first lookup table including a plurality of candidate first approximation values. A first correction coefficient is determined using the first plurality of bits as an index to a second lookup table including a plurality of candidate first correction coefficients. A second correction coefficient is determined by using the first plurality of bits as an index to a third lookup table including a plurality of candidate second correction coefficients. A second approximation value of the function is determined based on the first approximation value, the first correction coefficient, and the second plurality of bits.

Abstract: Provided are a method, a system, a computer program product, an Application Specific Integrated Circuit, and a cryptographic module, where a partitioning is performed of a SHA-2 state update into three blocks. A set of operations associated with the three blocks are executed in a pipelined manner, where each block feeds back for computation into itself.

Abstract: Correction of outliers in a data set includes receiving a first set of inputs of an input dataset requiring positive correction; and receiving a second set of inputs of the input dataset requiring negative correction. Conjunctive clauses with a predetermined number of terms that make all members in the second set of inputs false are identified to form a set of identified conjunctive clauses. Members from the first set of inputs that evaluate to true are collected for each conjunctive clause in the set of identified clauses. The set of identified conjunctive clauses are iterated through until all of the first set of inputs evaluates to true, and the conjunctive clauses are disjuncted to form a disjuncted expression. A correction circuit for the input dataset is generated based on the disjuncted expression.

Abstract: Accelerated approximations of functions, including: approximating, by a computing device, a hyperbolic tangent function applied to an input by: where the input is less than zero: performing a first exponentiation comprising raising a first base of two to a first exponent equal to double the input; and subtracting one from a result of the first exponentiation; and where the input is greater than zero, subtracting from one a result of a second exponentiation comprising raising a second base of two to a second exponent equal to a negative of double the input.

Abstract: A multi-operation computer instruction is executed to obtain an intermediate result. The execution includes selecting digits of a plurality of digits of multiple values to be multiplied. A location defined to hold a digit is greater in size than the size of the digit and further defined to hold a carry digit. The digits are selected from a predefined group of digits of a plurality of predefined groups based on a selection control of the instruction. The digits selected are multiplied to obtain a plurality of results. At least one result may be shifted a preselected amount to obtain at least one shifted result. One or more results and any shifted results, at least, are added to obtain an intermediate result. Execution of the instruction is repeated for multiple other predefined groups providing a plurality of intermediate results used to obtain a product of multiplying the multiple values.

Abstract: Hardware-implemented deep fraction polynomial evaluation includes receiving a floating-point input value to be input to a function with an approximation that includes a polynomial, and converting the floating-point input value to a fixed-point representation including a whole number portion, a leading fraction bits portion, and a remaining fraction bits portion. A first result is computed based on the whole number portion and the leading fraction bits portion using a first computation operation. A second result is computed based on the remaining fraction bits portion using a second computation operation, the second computation operation using a single fixed-point multiply-add instruction defining one or more fused multiply-add operations including a predetermined number of bit shifts with predetermined shift amounts. An output value of the function is computed based on the first result and the second result.

Abstract: A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

Abstract: A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a Galois multiply instruction. The execution unit includes a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product. The execution unit further includes a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product. The execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction.

Abstract: A processor includes an execution unit for executing a message padding instruction including an operand field indicating a register buffering a message block segment of a message block to be padded and a mode field indicating which hash functions is to be applied to the message block. The execution unit includes a padding circuit configured to receive a message block segment from a register indicated by the operand field, where the message block spans multiple registers in a register file. Based on which hash function is indicated by the mode field, the padding circuit selects a byte location in the message block segment at which to insert at least one padding byte and inserts the at least one padding byte at the byte location within the message block segment. The message block segment as padded by the at least one padding byte is written back to the register file.

Abstract: In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.

Abstract: A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a key-generating instruction. The execution unit includes a key generation circuit that, responsive to a key-generating instruction, iteratively applies a cryptographic function to a sequence of iteration inputs beginning with an encryption key obtained from the architected register file and stores, within the architected register file, a decryption key obtained from at least one iteration of the cryptographic function.

Abstract: Generation of test data for verifying a modular correction of a modular multiplication performed by a multiplier unit for very wide operands includes performing, by a multiplier unit using a computer, a modular multiplication by correcting a binary multiplication of two operands by a coarse-grained and a fine-grained correction. The computer selects adjacent intervals of the intermediate result, defines a sub-interval closely around a boundary between the adjacent intervals, and selects a value in the sub-interval. Moreover, the computer uses a first factorization algorithm for the value V for determining operands A?, B?, where the modular multiplication result of the operands corrected by the coarse-grained correction is in the sub-interval. The computer repeatedly determines A? plus varying ?-values as A? values, and determines B? values, so that the modular multiplication corrected by the coarse-grained correction is in the sub-interval.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be “don't care” terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.

Abstract: A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes converting one part of the input value to provide a converted value, performing one or more arithmetic operations on another part of the input value to provide an intermediate value, and using the converted value and the intermediate value to provide a converted result in the other format. The converting, the performing and the using are performed as part of executing the instruction. The converted result in the other format is to be used in processing within the computing environment.

Abstract: A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes scaling the input value to provide a scaled result and converting the scaled result from the one format to provide a converted result in the other format. The scaling and converting are to be performed as part of executing the instruction. The converted result in the other format is provided to be used in processing within the computing environment.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A plurality of linear algebra operations is repeated in parallel within the compute array to update a result matrix in an accumulator register based on the first input matrix, the second input matrix, and a number of rank updates of the result matrix to store in the accumulator register.

Abstract: An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.