Patents by Inventor Melvin T. Isom, III

Melvin T. Isom, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7421667
    Abstract: A system and method for enabling a vendor mode on an integrated circuit. A method is disclosed for applying a potential to a no-connect pin, whose function is unknown to the customer, to prevent the accidental enabling of the vendor mode. Applying the potential to the no-connect pin while concurrently applying a distinct sequence of logic values to other pins signals the deliberate intention to activate the vendor mode.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: September 2, 2008
    Assignee: Infineon Technologies AG
    Inventors: Melvin T. Isom, III, Shailesh U. Hegde
  • Patent number: 7055069
    Abstract: An integrated circuit (“IC”) package includes an input/output (“I/O”), a spare I/O circuit, and a resident IC for processing data. The I/O circuit is coupled with a plurality of external pins, which provide external electrical connections for the communication of data and information between the resident circuitry and external circuits, such as system logic and other electronic devices to which the IC package is coupled. The I/O circuit provides a data path between the I/O pins and the resident IC. The I/O circuit may include a data buffer and voltage and current surge protection to the IC package. The resident IC includes the primary IC electronic components, such as latches, gates, and processors, configured to process the data. The spare I/O circuit provides a redundant connection between the resident IC and the external circuits.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 30, 2006
    Assignee: Infineon Technologies AG
    Inventors: Melvin T. Isom, III, Shailesh U. Hegde
  • Patent number: 6983430
    Abstract: A system and method for resolving mismatched parameters in computer-aided design of integrated circuits during schematic migration. The system compares the parameters within the circuit primitives of the target and source schematic databases and detects if the parameters are different. If so, the system alters the parameter in the target circuit primitive to resolve the mismatch.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: January 3, 2006
    Assignee: Infineon Technologies AG
    Inventors: Shailesh U. Hegde, Melvin T. Isom, III
  • Patent number: 6968518
    Abstract: A system and method is presented for resolving missing graphical symbols in computer-aided design of integrated circuits during schematic migration. The system inserts a substitute target graphical symbol for the missing graphical symbol, or creates and inserts a dummy target symbol, such as a resistor network that maintains the electrical continuity of the target schematic.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: November 22, 2005
    Assignee: Infineon Technologies AG
    Inventors: Shailesh U. Hegde, Melvin T. Isom, III
  • Patent number: 6950995
    Abstract: A system and method for resolving mismatched graphical symbols in computer-aided design of integrated circuits during schematic migration. The system compares the dimensions of the graphical symbols within the circuit primitives of the target and source schematic databases and detects if the parameters are different. If so, the system alters the graphical symbols in the target circuit primitive to resolve the mismatch.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: September 27, 2005
    Assignee: Infineon Technologies AG
    Inventors: Shailesh U. Hegde, Melvin T. Isom, III
  • Patent number: 6813748
    Abstract: A system and method for enabling a vendor mode on an integrated circuit. A method is disclosed for applying a potential to a no-connect pin, whose function is unknown to the customer, to prevent the accidental enabling of the vendor mode. Applying the potential to the no-connect pin while concurrently applying a distinct sequence of logic values to other pins signals the deliberate intention to activate the vendor mode.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: November 2, 2004
    Assignee: Infineon Technologies AG
    Inventors: Melvin T. Isom, III, Shailesh U. Hegde