Abstract: A high temperature furnace comprising hot zone insulation having at least one shaped thermocouple assembly port to reduce temperature measurement variability is disclosed. The shaped thermocouple assembly port has an opening in the insulation facing the hot zone that is larger than the opening on the furnace shell side of the insulation. A method for producing a crystalline ingot in a high temperature furnace utilizing insulation having a shaped thermocouple assembly port is also disclosed.

Abstract: A high temperature furnace comprising hot zone insulation having at least one shaped thermocouple assembly port to reduce temperature measurement variability is disclosed. The shaped thermocouple assembly port has an opening in the insulation facing the hot zone that is larger than the opening on the furnace shell side of the insulation. A method for producing a crystalline ingot in a high temperature furnace utilizing insulation having a shaped thermocouple assembly port is also disclosed.

Abstract: A high temperature furnace comprising hot zone insulation having at least one shaped thermocouple assembly port to reduce temperature measurement variability is disclosed. The shaped thermocouple assembly port has an opening in the insulation facing the hot zone that is larger than the opening on the furnace shell side of the insulation. A method for producing a crystalline ingot in a high temperature furnace utilizing insulation having a shaped thermocouple assembly port is also disclosed.

Abstract: Methods and apparatus for controlling critical races in sequential circuits so that the there are no conflicts when two or more different data signals exists on shared circuit paths. This enables the design and implementation of sequential circuits having fewer gates than conventional circuit designs of equivalent function that translates into smaller area and power consumption. The control of the critical race is accomplished by adjusting the relative delay of the individual sections of one or more loops.

Abstract: Methods and apparatus for controlling critical races in sequential circuits so that the there are no conflicts when two or more different data signals exists on shared circuit paths. This enables the design and implementation of sequential circuits having fewer gates than conventional circuit designs of equivalent function that translates into smaller area and power consumption. The control of the critical race is accomplished by adjusting the relative delay of the individual sections of one or more loops.

Abstract: A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.

Abstract: A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.

Abstract: A munitions cartridge transmitter capable of emitting an electromagnetic signal after discharge from a cartridge propelling device comprises a signal generator, an electromagnetic signal transmitter coupled to the generator, an antenna coupled to the transmitter, and a hollow cartridge for housing the generator, the transmitter, and the antenna. The transmitter is energized after discharge of the cartridge propelling device by a power source contained in the cartridge.

Abstract: A CMOS programmable logic array includes a logical AND plane receiving a first group of input logic signals for forming a second group of logic minterms, and a logical OR plane receiving the logic minterms for forming a third group of output logic signals. Each type of logical plane contains a plurality of logic gates. Each plane type can be formed from the other plane type by the addition of a logic inverter to each input, and output of, that other-type plane. Interconnections determine the combination of input signals used to define the logic equation of the signal at the output of each logic gate of each plane. Static latches are used to retain the states of input and minterm logic signals. Logic planes and latches can be operated responsive to a two-phase clock signal.