Abstract: Methods and apparatuses supporting an electrical connection in a manner that eliminates or reduces a danger of electrical sparking are disclosed. A sparkless electrical connector has a conductor, configured to provide flow of electricity between an electrical source and a load, and a resistive element, operatively coupled to the conductor, to resist flow of electricity during a state of partial connection with the electrical source or the load. The resistive element may be not in contact with a terminal of the source or load during a state of full connection. The resistive element may be a coating of an anodized material on a pin of the conductor. The coating provides a resistance sufficient to prevent sparking during connection of the conductor and at least one of the electrical source and the load. Techniques disclosed herein benefit users and manufacturers in the areas of safety, cost, simplicity, and reliability.

Abstract: A power device having illuminated power outlets is disclosed. The power device includes a housing, a power input interface to the housing, and a plurality of power outlets on the housing for distributing power from the input. Within the housing of the power device, a printed circuit board has at least one LED positioned adjacent to at least one of the plurality of outlets to illuminate the openings of the outlets from within the interior housing.

Abstract: Methods and apparatus supporting an electrical connection are disclosed. Systems previously equipped with wire interfaces, such as battery terminals, can be equipped with a connector assembly to significantly reduce a hazard of electrical shock to a user. The connector assembly includes a stress relief component that attenuates a force, applied to the stress relief component, to reduce its effect on the connector assembly. By attenuating the force, the connector assembly maintains a substantially fixed position relative to the battery pack component and mitigates a potential for disruption in electrical connectivity. Techniques disclosed herein benefit users of battery packs or other devices as well as manufacturers by increasing safety, reliability, and ergonomics.

Abstract: A programmable device is provided, comprising a memory for storage of an encrypted boot loader, and a processing unit coupled to the memory. In the processing unit, a boot straper decrypts the encrypted boot loader into a plurality of boot loader instructions when the programmable device is initialized. A core executes boot loader instructions to accordingly load and execute an operation system.

Abstract: A bad block identification method for a memory is provided. The memory includes at least one memory block for storing data. A data decoding function is performed to the data, and it is determined whether the data decoding function was performed successfully. If the data decoding function was not performed successfully, at least one predetermined location in the memory block is checked. It is determined whether the predetermined location is marked by predetermined information. If the predetermined location is not marked by the predetermined information, the memory block is identified as a bad block.

Abstract: An optical disc recording system comprises a front-end volatile memory, a back-end non-volatile memory, and a front-end processor. The front-end volatile memory stores sector data. The back-end non-volatile memory stores front-end codes and back-end codes. The front-end processor downloads the front-end codes from the back-end non-volatile memory to the front-end volatile memory, and accesses the sector data in the front-end volatile memory during optical disc recording.

Abstract: A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (H3PO4), nitric acid (HNO3), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.

Abstract: A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (H3PO4), nitric acid (HNO3), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.

Abstract: A method for forming a top interconnection level and bonding pads for an integrated circuit chip is described. The interconnection level is formed by a damascene type process. Bonding pads are placed above the plane of the wiring channels of the interconnection level. This eliminates the problem of dishing of the relatively large bonding pads which occurs, during chemical mechanical polishing, when the bonding pads are on the same level as the interconnection metallurgy. The interconnection wiring includes a smaller pad base segment upon which the larger bonding pad is then formed. The bonding pad base segments are small enough that dishing during CMP is not a problem. Placing the bonding pads on pad bases provides for a more robust pad. The top level and bonding pad fabrication procedures are applicable with various conductive materials including aluminum, tungsten, and copper.

Abstract: The invention teaches the creation of borderless contact holes by using multiple layers of overlying dielectric, having different, interdependent etch rates, that function as etch stop layers for the creation of the borderless contact holes through a layer of overlying dielectric.

Abstract: A process for producing a self-aligned contact comprises the steps of forming leads on a substrate, forming an etching stop layer on the leads by depositing, then forming a sacrificed oxide layer; after the structure of the leads is defined, a spacer is formed on both sides of the structure; a sacrificed oxide layer is formed, allowing the spacer to protrude in the form of horn. Next, a dielectric layer having a flat upper surface is deposited on the substrate and the structure of leads, a contact hole being formed between the leads so as to connect the substrate, a conductive material being filled in the contact hole to form a plug.

Abstract: A method of manufacturing a double gate oxide layer. A substrate has trenches that divide the substrate into a memory circuit region and a logic circuit region. A dielectric layer is formed on the substrate to fill the trenches. The dielectric layer of the logic region is removed, thereby exposing the substrate. An ion implantation step is performed on the substrate of the logic circuit region using a reverse tone mask. A conformal barrier layer is formed over the substrate. A spin-on layer is formed over the barrier layer. A chemical mechanical polishing step is performed to remove the in-on layer, the barrier layer, and dielectric layer outside the trenches, thereby exposing the substrate. A thermal oxidation step is performed to form a double gate oxide layer that is thicker in the logic circuit region than it is in the memory circuit region.

Abstract: A method for forming a top interconnection level and bonding pads for an integrated circuit chip is described. The interconnection level is formed by a damascene type process. Bonding pads are placed above the plane of the wiring channels of the interconnection level. This eliminates the problem of dishing of the relatively large bonding pads which occurs, during chemical mechanical polishing, when the bonding pads are on the same level as the interconnection metallurgy. The interconnection wiring includes a smaller pad base segment upon which the larger bonding pad is then formed. The bonding pad base segments are small enough that dishing during CMP is not a problem. Placing the bonding pads on pad bases provides for a more robust pad. The top level and bonding pad fabrication procedures are applicable with various conductive materials including aluminum, tungsten, and copper.