Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.

Abstract: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.

Abstract: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.

Abstract: A back-array, full-direction, circular polarization antenna is disclosed to include a power divider, which has two input contact holes and an output contact hole respectively electrically connected to an internal circuit thereof, and two patch antennas respectively symmetrically connected to two opposite sides of the power divider to produce two electric fields with a 90-degrees phase difference kept between the mechanical degrees and the electric degrees produced by each electric field, each patch antenna having a patch-like ceramic body, a radiation metal electrode printed on one side of the patch-like ceramic body, and a metal contact pin affixed to the radiation metal electrode and the patch-like ceramic body and connected to one input contact hole of the power divider.

Abstract: A back-array, full-direction, circular polarization antenna is disclosed to include a power divider, which has two input contact holes and an output contact hole respectively electrically connected to an internal circuit thereof, and two patch antennas respectively symmetrically connected to two opposite sides of the power divider to produce two electric fields with a 90-degrees phase difference kept between the mechanical degrees and the electric degrees produced by each electric field, each patch antenna having a patch-like ceramic body, a radiation metal electrode printed on one side of the patch-like ceramic body, and a metal contact pin affixed to the radiation metal electrode and the patch-like ceramic body and connected to one input contact hole of the power divider.

Abstract: A circuit for generating a reference voltage of an image sensor is provided. The circuit comprises a signal differential amplifier, a gain amplifier, a source follower and a clamp circuit. The signal differential amplifier is adapted for receiving and comparing a bias voltage and the reference voltage, and outputting a first voltage according to a comparison result. The gain amplifier is coupled to the signal differential amplifier, and is adapted for receiving the first voltage and outputting a second voltage. The source follower, coupled to the gain amplifier, and is adapted for receiving the second voltage and outputting the reference voltage. The clamp circuit is coupled to the source follower, and is adapted for receiving the reference voltage and limiting the reference voltage to below a clamp voltage.

Abstract: A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.

Abstract: A circuit for generating a reference voltage of an image sensor is provided. The circuit comprises a signal differential amplifier, a gain amplifier, a source follower and a clamp circuit. The signal differential amplifier is adapted for receiving and comparing a bias voltage and the reference voltage, and outputting a first voltage according to a comparison result. The gain amplifier is coupled to the signal differential amplifier, and is adapted for receiving the first voltage and outputting a second voltage. The source follower, coupled to the gain amplifier, and is adapted for receiving the second voltage and outputting the reference voltage. The clamp circuit is coupled to the source follower, and is adapted for receiving the reference voltage and limiting the reference voltage to below a clamp voltage.

Abstract: An active pixel sensor comprises a first voltage source and a second voltage source. The first voltage source is provided to charge a photoelectric element. The second voltage source is provided to supply power to a source follower transistor, a read out switch transistor, and a bias transistor. The first voltage source and the second voltage source are different, such that the noise of voltage signal on the photoelectric diode can be processed individually, and the switching noise is small and can be processed easily. Moreover, the flexibility of the voltage variation can be increased, and the two voltage sources may be individually adjusted as desired.

Abstract: A multi-layer piezoelectric center-drive ceramic transformer includes a stack of piezoelectric ceramic blanks sintered together, each piezoelectric ceramic blanks having at least one odd-number layer and at least one even-number layer alternatively sandwiched in between a top cover layer and a bottom cover layer, first and second inner electrode layers reversely printed on the at least one odd-number layer, third and fourth inner electrode layers reversely printed on the at least one even-number layer, first and second output terminal electrodes respectively printed on two distal ends of each piezoelectric ceramic blank, and first and second input terminal electrodes respectively printed on two opposite lateral sides of each piezoelectric ceramic blank, the first input terminal electrodes being respectively connected to the first inner electrode layers and the third inner electrode layers, the second input terminal electrodes being respectively connected to the second inner electrode layers and the fourth inn