Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.

Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a portion of the photoresist corresponding to a portion of the first stitching region is unexposed during the first light-exposure. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region and a functional feature in the second stitching region, and the portion of the photoresist is exposed by the functional feature during the second light-exposure.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a portion of the photoresist corresponding to a portion of the first stitching region is unexposed during the first light-exposure. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region and a functional feature in the second stitching region, and the portion of the photoresist is exposed by the functional feature during the second light-exposure.

Abstract: A package including a device die and an encapsulant is provided. The device die includes a semiconductor substrate, an interconnect structure, a conductive via, and a dielectric layer. The interconnect structure is disposed over the semiconductor substrate. The conductive via is disposed over and electrically coupled to the interconnect structure. The dielectric layer is disposed over the interconnect structure and laterally encapsulating the conductive via, wherein the dielectric layer includes a sidewall and a bottom surface facing the interconnect structure, and the sidewall of the dielectric layer is tilted with respect to the bottom surface of the dielectric layer. The encapsulant laterally encapsulates the device die.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: A semiconductor device includes a dielectric layer and a conductive structure in the dielectric layer. The dielectric layer includes a dielectric material and a compound represented by Chemical Formula 1. In Chemical Formula 1, R is the same as defined in the specification.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of through insulating vias (TIV), a plurality of dipole antennas, and a second redistribution structure. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The TIVs and the dipole antennas are embedded in the encapsulant. Each dipole antenna includes a pair of antenna elements. Each antenna element has a first folded-sidewall and a second folded-sidewall opposite to the first folded-sidewall. A portion of each second folded-sidewall in the pair of antenna elements face each other. Each first folded-sidewall includes at least three sub-sidewalls connected to each other. The adjacent sub-sidewalls form an obtuse angle. The second redistribution structure is disposed on the die, the TIVs, the dipole antennas, and the encapsulant.

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of through insulating vias (TIV), a plurality of dipole antennas, and a second redistribution structure. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The TIVs and the dipole antennas are embedded in the encapsulant. Each dipole antenna includes a pair of antenna elements. Each antenna element has a first folded-sidewall and a second folded-sidewall opposite to the first folded-sidewall. A portion of each second folded-sidewall in the pair of antenna elements face each other. Each first folded-sidewall includes at least three sub-sidewalls connected to each other. The adjacent sub-sidewalls form an obtuse angle. The second redistribution structure is disposed on the die, the TIVs, the dipole antennas, and the encapsulant.

Abstract: A semiconductor device includes a dielectric layer and a conductive structure in the dielectric layer. The dielectric layer includes a dielectric material and a compound represented by Chemical Formula 1.

Abstract: Semiconductor devices, semiconductor packages and methods of forming the same are provided. One of the semiconductor device includes a dielectric layer and a connector. The dielectric layer includes a dielectric material and an additive, wherein the additive includes a compound represented by Chemical Formula 1. The connector is disposed in the dielectric layer.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: Semiconductor devices, semiconductor packages and methods of forming the same are provided. One of the semiconductor device includes a dielectric layer and a connector. The dielectric layer includes a dielectric material and an additive, wherein the additive includes a compound represented by Chemical Formula 1. The connector is disposed in the dielectric layer.