Abstract: Provided is an anti-Henipavirus monoclonal antibody having broad spectrum neutralization activity, wherein the antibody comprises a macaque variable region and a human constant region. The antibody of the present invention has good binding activity to both Nipah virus glycoprotein G and Hendra virus glycoprotein G, can effectively neutralize Nipahpseudovirus and Hendra pseudovirus, and can be used for preparing drugs for treating Henipavirus diseases.

Abstract: A method for recording human motion performing a task with a tool and training a robot to perform the task, including the steps of performing tracker calibration without the robot present, performing teaching tool calibration with the robot present and placed at a predetermined location, and performing training without the robot present.

Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

Abstract: A display panel, including a drive circuit, where the drive circuit is at least used to drive the display panel to display obtained display data. The drive circuit includes a shift register, a data buffer and a first control circuit; the shift register is used to output display data of each sub-pixel according to a preset timing sequence; the data buffer at least includes a first cache module composed of N repeat units; a repeat unit includes at least one cache unit, the cache unit is connected to the shift register, and two cache units at a same position in the k-th repeat unit and the (k+1)-th repeat unit are multiplexed with a same clock signal terminal; the cache unit is used to be turned on in response to an output signal from the clock signal terminal connected to the cache unit, to cache the received display data.

Abstract: The present disclosure relates to the field of warehousing logistics. Provided are a supplies counting method and apparatus, and a device and a storage medium. An implementation solution involves: in response to receiving a counting task for supplies in a warehouse, determining a goods grid in which a material container corresponding to the counting task is located; sending the goods grid, in which the material container is located, to a target automated guided vehicle, so that the target automated guided vehicle performs path planning and then acquires identifiers of materials in the material container; in response to receiving the identifiers of the materials in the material container that are sent by the target automated guided vehicle, performing statistics on the identifiers; and comparing a statistical result with a storage result of the materials in the material container, and determining a supplies counting result according to a comparison result.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric layer disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure, wherein the interconnect structure laterally connects to at least one edge of the 2D conductive structure.

Abstract: A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.

Abstract: The present application provides a catalyst for copolymerization of ethylene and methyl methacrylate and an application thereof. The catalyst includes a main catalyst, and the main catalyst is obtained by compounding a compound of formula (I) and a compound of formula (II); a mole ratio of the compound of formula (I) to the compound of formula (II) is (1:49) to (49:1). The catalyst has an excellent catalytic activity, and a copolymer of ethylene and methyl methacrylate with a high molecular weight can be obtained, with a weight average molecular weight of not less than 1×105 g/mol.

Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

Abstract: Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells including a first string of memory cells and a second string of memory cells; and a first switch including: a first electrode connected to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells, and a second electrode connected to a first global bit line, wherein gate electrodes of the first string of memory cells are connected to a first word line and gate electrodes of the second string of memory cells are connected to a second word line.

Abstract: The present application provides an adjustable radio frequency unit, a filter, and an electronic device. The adjustable radio frequency unit includes a first tunable dielectric layer and a second tunable dielectric layer; a first conductive layer located between the first tunable dielectric layer and the second tunable dielectric layer; a second conductive layer located on the side, away from the first conductive layer, of the first tunable dielectric layer; and a third conductive layer located on the side, away from the first conductive layer, of the second tunable dielectric layer; wherein orthographic projections of the first conductive layer, the second conductive layer and the third conductive layer on the first tunable dielectric layer at least partially overlap with one another. The adjustable radio frequency unit has the characteristic of passband adjustability and with high adjustment precision, good controllability, wide working frequency range, and low loss and cost.

Abstract: The present disclosure discloses a control method for an energy storage system and apparatus, an energy storage system, and an energy storage device. The control method includes obtaining an operation parameter of a power grid and an electric quantity state of an energy storage battery in an energy storage system; and controlling working states of the power grid, the energy storage battery, a first auxiliary power supply, and a second auxiliary power supply according to the operation parameter of the power grid and the electric quantity state of the energy storage battery.

Abstract: The present disclosure relates to a method for protecting DC line impedance phase based on protection and control coordination, and an application scenario of the method for protecting is a three-terminal flexible DC transmission network. The method uses high controllability of a converter after a fault, injects a characteristic signal at a characteristic frequency, and calculates a phase angle of input impedance to determine a fault interval, which effectively improves protection performance, turns passive to active, and is not affected by nonlinearity of the converter. At the same time, compared with a full-bridge MMC, using a half-bridge MMC does not need to perform fault ride-through first when identifying a fault, and does not need to add additional equipment, it creates fault features and can reliably identify an fault interval; improves protection quickness and at the same time also has better economic benefits.

Abstract: A forming control method for a resistive random-access memory cell array is provided. While a forming action of the resistive random-access memory cell array is performed, a verification action is performed to judge whether the forming action on the resistive random-access memory cells has been successfully done. By properly changing a forming voltage or a pulse width, the forming actions on all of the resistive random-access memory cells of the resistive random-access memory cell array can be successfully done.

Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.

Abstract: An apertured nonwoven web is provided. The apertured nonwoven web comprises carded fibers, a first side, and a second side. The apertured nonwoven web defines a plurality of apertures therein. The apertures may each have a first side aperture size and a second side aperture size, and a ratio of the first side aperture size to the second side aperture size may be between about 1.15:1 to about 1:1.15. The plurality of apertures may have an aperture size regularity of about 1% to about 15%. The plurality of apertures may have an aperture shape regularity between about 1% to about 12%.

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Abstract: There is provided a phase shifter having a phase shift region and a peripheral region, and including a first substrate, a second substrate and a dielectric layer between such two substrates; the first substrate includes a first dielectric substrate, a first electrode and a first auxiliary structure; the second substrate includes a second dielectric substrate, a second electrode and a second auxiliary structure; the phase shift region includes overlapping regions; the first electrode and the second electrode are located in the phase shift region, and have orthographic projections, on the first dielectric substrate, overlapped at least partially in the overlapping regions; the first auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the first dielectric substrate; the second auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the second dielectric substrate.

Abstract: A person's privacy is protected by the law in many settings and disclosed herein are systems, methods, and instrumentalities associated with anonymizing an image of a person while still preserving the visual saliency and/or utility of the image for one or more downstream tasks. These objectives may be accomplished using various machine-learning (ML) techniques such as ML models trained for extracting identifying and residual features from the input image as well as ML models trained for transforming the identifying features into identity-concealing features and for preserving the utility features of the image. An output image may be generated based on the various ML models, wherein the identity of the person may be substantially disguised in the output image while the background and utility attributes of the original image may be substantially maintained in the output image.