Patents by Inventor MENG CHEN YANG

MENG CHEN YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10761511
    Abstract: A printing method for biochip fabrication is implemented by a printing apparatus including a platform for supporting a substrate, a pipet module, and a control module. The method includes: moving the platform in sequence to multiple positions associated with multiple to-be-printed points on the platform; moving the pipet module reciprocatively toward and away from the platform during each movement of the platform; discharging, by the pipet module, solution sample onto the respective one of the to-be-printed points to form a bio-sensing spot to form a biochip; and determining, by the control module, whether to execute a supplementary printing procedure for the biochip based on whether each bio-sensing spot satisfies a predetermined criterion.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Syuan-Yi Chen, Meng-Chen Yang, Kai-Wen Chuang, Ren-Bin Lai
  • Publication number: 20190243337
    Abstract: A printing method for biochip fabrication is implemented by a printing apparatus including a platform for supporting a substrate, a pipet module, and a control module. The method includes: moving the platform in sequence to multiple positions associated with multiple to-be-printed points on the platform; moving the pipet module reciprocatively toward and away from the platform during each movement of the platform; discharging, by the pipet module, solution sample onto the respective one of the to-be-printed points to form a bio-sensing spot to form a biochip; and determining, by the control module, whether to execute a supplementary printing procedure for the biochip based on whether each bio-sensing spot satisfies a predetermined criterion.
    Type: Application
    Filed: October 31, 2018
    Publication date: August 8, 2019
    Applicant: National Taiwan Normal University
    Inventors: Syuan-Yi CHEN, Meng-Chen YANG, Kai-Wen CHUANG, Ren-Bin LAI
  • Patent number: 10209998
    Abstract: A processor includes an execution unit, a retirement module, a first retirement counter, a second retirement counter, and an adjustment module. The execution unit executes instructions of a first thread and a second thread by simultaneous multithreading. The retirement module retires the executed instructions of the first thread in order of the first-thread instruction sequence, and retires the executed instructions of the second thread in order of the second-thread instruction sequence. The first retirement counter determines a first multi-thread retirement rate of the first thread. The second retirement counter determines a second multi-thread retirement rate of the second thread. The adjustment module adjusts the proportions of hardware resources respectively occupied by the first thread and the second thread according to the first multi-thread retirement rate and the second multi-thread retirement rate, so that the processor executes at its most efficient level of performance.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 19, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Meng-Chen Yang
  • Patent number: 10044829
    Abstract: Control systems and methods for cache coherency are provided. One control method includes steps of transmitting a link-connect request to a second electrical device when the first electrical device is coupled to the second electrical device by a cache coherency (CC) interface by a first electrical device, establishing a link between the first electrical device and second electrical device according to the link-connect request by the CC interface, and operating a first operating system of the first electrical device by a second processing unit of the second electrical device after establishing the link.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: August 7, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Jiin Lai, Meng-Chen Yang
  • Patent number: 9891923
    Abstract: A loop predictor trains a branch instruction to determine a trained loop count of a loop. When the loop fits in an instruction buffer, the processor stops fetching from an instruction cache, sends the loop instructions to an execution engine from the buffer without fetching from the cache, maintains a loop pop count of times the branch is sent to the execution engine from the buffer, and predicts the branch instruction is taken when the loop pop count is less than the trained loop count and otherwise predicts not taken.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: February 13, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Guo Hua Chen, Meng Chen Yang, Xin Yu Gao, Fan Gong Gong, Zhen Hua Huang
  • Publication number: 20170364361
    Abstract: A processor includes an execution unit, a retirement module, a first retirement counter, a second retirement counter, and an adjustment module. The execution unit executes instructions of a first thread and a second thread by simultaneous multithreading. The retirement module retires the executed instructions of the first thread in order of the first-thread instruction sequence, and retires the executed instructions of the second thread in order of the second-thread instruction sequence. The first retirement counter determines a first multi-thread retirement rate of the first thread. The second retirement counter determines a second multi-thread retirement rate of the second thread. The adjustment module adjusts the proportions of hardware resources respectively occupied by the first thread and the second thread according to the first multi-thread retirement rate and the second multi-thread retirement rate, so that the processor executes at its most efficient level of performance.
    Type: Application
    Filed: August 5, 2016
    Publication date: December 21, 2017
    Inventor: Meng-Chen YANG
  • Publication number: 20160156734
    Abstract: Control systems and methods for cache coherency are provided. One control method includes steps of transmitting a link-connect request to a second electrical device when the first electrical device is coupled to the second electrical device by a cache coherency (CC) interface by a first electrical device, establishing a link between the first electrical device and second electrical device according to the link-connect request by the CC interface, and operating a first operating system of the first electrical device by a second processing unit of the second electrical device after establishing the link.
    Type: Application
    Filed: June 16, 2015
    Publication date: June 2, 2016
    Inventors: Jiin LAI, Meng-Chen YANG
  • Publication number: 20160092230
    Abstract: A loop predictor trains a branch instruction to determine a trained loop count of a loop. When the loop fits in an instruction buffer, the processor stops fetching from an instruction cache, sends the loop instructions to an execution engine from the buffer without fetching from the cache, maintains a loop pop count of times the branch is sent to the execution engine from the buffer, and predicts the branch instruction is taken when the loop pop count is less than the trained loop count and otherwise predicts not taken.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 31, 2016
    Inventors: GUO HUA CHEN, MENG CHEN YANG, XIN YU GAO, FAN GONG GONG, ZHEN HUA HUANG