Patents by Inventor Meng-Chi Chen

Meng-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating a dual-damascene copper structure
    Patent number: 7538024
    Abstract: A method for fabricating a dual-damascene copper structure includes providing a semiconductor substrate having a dielectric layer thereon and a dual-damascene hole positioned in the dielectric layer, wherein a portion of the semiconductor substrate is exposed in the dual-damascene hole. A PVD process and an atomic CVD process are sequentially performed to form a substrate-protecting layer and a tantalum nitride layer in the dual-damascene hole. And then a copper layer is formed in the dual-damascene hole.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: May 26, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Hsien-Che Teng, Chin-Fu Lin, Meng-Chi Chen
  • COPPER DAMASCENE PROCESS
    Publication number: 20080026579
    Abstract: A copper damascene process includes providing a substrate having a dielectric layer thereon, forming at least a copper damascene structure in the dielectric layer, performing a heat treatment on the substrate, and performing a reduction plasma treatment on a surface of the copper damascene structure. The impurities formed in the copper damascene process are removed by the heat treatment, therefore the copper damascene structure is completely reduced by the reduction plasma treatment and is improved.
    Type: Application
    Filed: July 25, 2006
    Publication date: January 31, 2008
    Inventors: Kuo-Chih Lai, Mei-Ling Chen, Jei-Ming Chen, Hsin-Hsing Chen, Shih-Feng Su, Meng-Chi Chen
  • METHOD OF FABRICATING A DUAL-DAMASCENE COPPER STRUCTURE
    Publication number: 20060252250
    Abstract: A method for fabricating a dual-damascene copper structure includes providing a semiconductor substrate having a dielectric layer thereon and a dual-damascene hole positioned in the dielectric layer, wherein a portion of the semiconductor substrate is exposed in the dual-damascene hole. A PVD process and an atomic CVD process are sequentially performed to form a substrate-protecting layer and a tantalum nitride layer in the dual-damascene hole. And then a copper layer is formed in the dual-damascene hole.
    Type: Application
    Filed: May 3, 2005
    Publication date: November 9, 2006
    Inventors: Hsien-Che Teng, Chin-Fu Lin, Meng-Chi Chen