Abstract: A semiconductor cell structure includes: a gate electrode extending in a first direction over a substrate; a first and a second power rails extending in a second direction different from the first direction in a first layer over the substrate, wherein the first power rail and the second power rail are disposed on opposite sides of the cell structure; first conductive segments extending in the second direction between the first and second power rails in the first layer; a third power rail extending in the first direction in a second layer over the first layer; and second conductive segments extending in the first direction in the second layer. At least two of the second conductive segments are aligned with a single track line in the cell structure in the first direction and are separated by a spacing substantially equal to or greater than a minimal segment end spacing.

Abstract: This invention discloses a dynamic memory allocation method for an Ethernet switching architecture, which can resolve problems with the limitations of transmission bandwidths and transmission port counts in a conventional network packet switching. The method comprises steps of providing a plurality of input ports and output ports, providing a shared memory for storing packet segments of a plurality of packets, providing a first link RAM (Random Access Memory) for controlling a making and reading of a single linked list for the packet segments of each the plurality of packets, and providing a second link RAM serving as a FIFO (first in first out) device for co-managing an obtaining of the link address spaces at the corresponding input ports before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.

Abstract: This invention discloses a dynamic memory allocation method for an Ethernet switching architecture, which can resolve problems with the limitations of transmission bandwidths and transmission port counts in a conventional network packet switching. The method comprises steps of providing a plurality of input ports and output ports, providing a shared memory for storing packet segments of a plurality of packets, providing a first link RAM (Random Access Memory) for controlling a making and reading of a single linked list for the packet segments of each the plurality of packets, and providing a second link RAM serving as a FIFO (first in first out) device for co-managing an obtaining of the link address spaces at the corresponding input ports before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.