Abstract: Described examples include an integrated circuit having a substrate, a first doped region in the substrate having a first conductivity type, and a first epitaxial layer on the substrate, wherein the first doped region extends into the first epitaxial layer. The integrated circuit also has a second doped region in the first epitaxial layer having the first conductivity type, a second epitaxial layer on the first epitaxial layer, wherein the second doped region extends into the second epitaxial layer. The integrated circuit also has a well in the second epitaxial layer having a second conductivity type, and a first active device formed in the well.

Abstract: A keyboard file verification method based on image processing comprises controlling a processor to perform following operations: obtaining a keyboard file; generating, according to the keyboard file, a search index and a feature image; obtaining a template image from a template database according to the search index; performing a calibration operation according to the feature image, wherein the calibration operation comprises: adjusting a resolution of the feature image according to a resolution of the template image; performing a shifting operation according to the feature image, to generate a plurality of candidate images; and comparing a key block of each of the plurality of candidate images with a key block of the template image to generate a difference map and a comparison result.

Abstract: GaN devices with a modified heterojunction structure and methods of making thereof are described. The GaN device comprises a heterojunction structure modified to include one or more deactivated regions. The heterojunction structure of the deactivated regions has different structural configurations than that of the as-grown heterojunction structure. The locally confined structural alteration of the heterojunction structure weakens or prohibits 2DEG formation in the deactivated regions. Moreover, the amount of net charges mapped to a field plate positioned above the heterojunction structure can be locally reduced or eliminated. Consequently, the electric field present between the heterojunction structure and the field plate can be reduced.

Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.

Abstract: An integrated circuit includes an epitaxial layer over a semiconductor substrate. The epitaxial layer has a first conductivity type and a top surface. First, second and third trenches are located in the epitaxial layer. The trenches respectively include first, second and third field plates. First and second body members are located within the epitaxial layer and have a different second conductivity type. The first body member is located between the first and second trenches, and the second body member is located between the second and third trenches. The first body member extends a first distance between the top surface and the substrate, and the second body member extends a lesser second distance between the top surface and the substrate.

Abstract: A trench gate metal oxide semiconductor (MOSFET) device includes a substrate with a semiconductor surface layer doped a first conductivity type. At least one trench gate MOSFET cell is located in or over the semiconductor surface layer, and includes a body region in the semiconductor surface layer doped a second conductivity type, and a source region on top of the body region doped the first conductivity type. A trench extends down from a top side of the semiconductor surface layer, the trench abutting the body region and being lined with a dielectric material. A field plate that includes polysilicon is located in the trench, and a gate electrode is located over the field plate. The field plate has a bottom portion, a middle portion, and a top portion, wherein the bottom portion is narrower than the middle portion, and the middle portion is narrower than the top portion.

Abstract: Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region.

Abstract: A semiconductor device includes first, second and third trenches formed in a semiconductor layer having a first conductivity type. Each trench includes a corresponding field plate and a corresponding gate over each field plate. A first body region having a second opposite conductivity type is between the first and second gates, and a second body region having the second conductivity type is located between the second and third gates. A first source region is located over the first body region and a second source region is located over the second body region, the first and second source regions having the first conductivity type. A first gate bus is conductively connected to the first gate and a second gate bus is conductively connected to the second gate, the first gate bus conductively isolated from the second gate bus.

Abstract: Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.

Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.

Abstract: An electronic device can include a semiconductor substrate having a front side and a back side; an emitter region closer to the front side than to the back side; a trench extending from a back side surface into the semiconductor substrate, wherein the trench has a sidewall and a bottom; a collector region along the back side surface and spaced apart from the bottom of the trench; a field-stop region lying along the bottom and at least a portion of the sidewall of the trench, wherein the emitter and field-stop regions have one conductivity type, and the collector region has the opposite conductivity type; and a collector terminal along the back side and including a metal-containing material, wherein the collector terminal contacts the collector region and is isolated from the field-stop region. A process of forming the electronic device does not require complex or marginal processing operations.

Abstract: Systems and methods herein are directed towards semiconductor devices and methods of manufacture thereof, including the formation of a plurality of passive trenches that act as a single passive trench and may be connected to gate electrodes and/or emitters in various embodiments.

Abstract: Systems and methods herein are directed towards semiconductor devices and methods of manufacture thereof, including the formation of a plurality of passive trenches that act as a single passive trench and may be connected to gate electrodes and/or emitters in various embodiments.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT device can also include a first mesa defined by a first sidewall of the trench and in parallel with the trench and a second mesa defined by a second sidewall of the trench and in parallel with the trench. The first mesa can include at least one active segment of the IGBT device and the second mesa can include at least one inactive segment of the IGBT device.

Abstract: A semiconductor device having a novel buried junction architecture. The semiconductor device may have three terminals and a drift region between two of the terminals. The drift region includes an upper drift layer, a lower drift layer, and a buried junction layer between the upper and lower drift layers, wherein the upper and lower drift layers have a first type of doping. The buried junction layer comprises an interspersed pattern of a first material and a second material, the first material having a second type of doping opposite the first type of doping and the second material having the first type of doping and having a different doping concentration than the upper and lower drift layers.