Patents by Inventor Meng-Chieh WEN

Meng-Chieh WEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11545619
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Hsiang Wang, Han-Ting Lin, Yu-Feng Yin, Sin-Yi Yang, Chen-Jung Wang, Yin-Hao Wu, Kun-Yi Li, Meng-Chieh Wen, Lin-Ting Lin, Jiann-Horng Lin, An-Shen Chang, Huan-Just Lin
  • Publication number: 20220271087
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A substrate having a cell region and a mark region is received. A dielectric layer is etched to expose a conductive line in the cell region and form a trench in the mark region. A conductive layer is formed over the cell region and in the trench. The conductive layer is etched to form a bottom electrode via in the cell region and a first mark layer in the trench.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Inventors: HAN-TING LIN, JIANN-HORNG LIN, HSING-HSIANG WANG, HUAN-JUST LIN, SIN-YI YANG, CHEN-JUNG WANG, KUN-YI LI, MENG-CHIEH WEN, LAN-HSIN CHIANG, LIN-TING LIN
  • Publication number: 20220029091
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Hsiang WANG, Han-Ting LIN, Yu-Feng YIN, Sin-Yi YANG, Chen-Jung WANG, Yin-Hao WU, Kun-Yi LI, Meng-Chieh WEN, Lin-Ting LIN, Jiann-Horng LIN, An-Shen CHANG, Huan-Just LIN