Abstract: A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.

Abstract: A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.

Abstract: A transceiving apparatus includes a transmitter module and receiver module. The transmitter module has a transmitting circuit and an auxiliary circuit. The transmitting circuit generates a first differential input signal pair when the transceiving apparatus operates in a transmitter mode (TX mode). The auxiliary circuit is coupled to the transmitting circuit, for generating a differential output signal pair according to the first differential input signal pair when the transceiving apparatus operates in the TX mode. The receiver module is coupled to the auxiliary circuit, for receiving a second differential input signal pair according to a common mode voltage when the transceiving apparatus operates in a receiver mode (RX mode). Herein the auxiliary circuit generates the common mode voltage when the transceiving apparatus operates in the RX mode.

Abstract: A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.

Abstract: The invention discloses a PVT-independent current-controlled oscillator, including a PV-controller, a current-controlled oscillator and a T-controller. The current-controlled oscillator is coupled to the PV-controller and outputs an oscillation frequency.

Abstract: A transceiving apparatus includes a transmitter module and receiver module. The transmitter module has a transmitting circuit and an auxiliary circuit. The transmitting circuit generates a first differential input signal pair when the transceiving apparatus operates in a transmitter mode (TX mode). The auxiliary circuit is coupled to the transmitting circuit, for generating a differential output signal pair according to the first differential input signal pair when the transceiving apparatus operates in the TX mode. The receiver module is coupled to the auxiliary circuit, for receiving a second differential input signal pair according to a common mode voltage when the transceiving apparatus operates in a receiver mode (RX mode). Herein the auxiliary circuit generates the common mode voltage when the transceiving apparatus operates in the RX mode.

Abstract: The invention discloses a PVT-independent current-controlled oscillator, including a PV-controller, a current-controlled oscillator and a T-controller. The current-controlled oscillator is coupled to the PV-controller and outputs an oscillation frequency.

Abstract: A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals.

Abstract: A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals.

Abstract: A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.