Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.

Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

Abstract: An ACF comprising a substrate, a layer of an adhesive on the surface of the substrate, the adhesive optionally having conductive particles dispersed therein, at least one tier of conductive particles arranged in a non-random array, the tier being formed by transfer of conductive particles from a carrier belt having a stitching line to the surface of the adhesive layer wherein the portion of the tier corresponding to the stitching line is free of conductive particles, and the adhesive layer being overcoated with a second tier of conductive particles arranged in a non-random array at least in the area of the first tier corresponding to the stitching line. The tiers may be at the same or different depths within the adhesive layer. More than two tiers of conductive particles may be present in the ACF.

Abstract: An ACF comprising a substrate, a layer of an adhesive on the surface of the substrate, the adhesive optionally having conductive particles dispersed therein, at least one tier of conductive particles arranged in a non-random array, the tier being formed by transfer of conductive particles from a carrier belt having a stitching line to the surface of the adhesive layer wherein the portion of the tier corresponding to the stitching line is free of conductive particles, and the adhesive layer being overcoated with a second tier of conductive particles arranged in a non-random array at least in the area of the first tier corresponding to the stitching line. The tiers may be at the same or different depths within the adhesive layer. More than two tiers of conductive particles may be present in the ACF.

Abstract: The present invention provides a method for fabricating a patterned structure in a semiconductor device, which includes the following processes. First, a target layer, a first mask and a first patterned mask are sequentially formed on a substrate. Then, a first etching process is performed to form a plurality of characteristic structures on the substrate, wherein each of the characteristic structures comprises a patterned first mask and a patterned target layer. A second patterned mask is formed on the substrate, wherein the second patterned mask covers a portion of the characteristic structures and exposes a predetermined region. A second etching process is performed to fully eliminate the characteristic structures within the predetermined region. Finally, a third etching process is performed to fully eliminate the target layer not covered by the patterned first mask.

Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: depositing a dielectric layer and a hard mask on surface of a semiconductor substrate; patterning the hard mask by forming an aperture in the hard mask; utilizing a gas containing CaXb and CdHXe to perform a pre-treatment on the patterned hard mask and the dielectric layer, in which a, b, d and e from CaXb and CdHXe are integers and X represents halogen atom; and performing an etching process to transfer the aperture into the dielectric layer.