Patents by Inventor Meng-Chyi Lin
Meng-Chyi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220300690Abstract: Embodiments of the present disclosure relate to a system and method for incremental compilation. The method includes identifying a change to a portion of a circuit design. The circuit design without the change was previously compiled to an FPGA. The method also includes configuring a transactor of the FPGA to simulate the portion of the circuit design with the change and configuring the FPGA to use the transactor to simulate the portion of the circuit design with the change.Type: ApplicationFiled: March 14, 2022Publication date: September 22, 2022Inventors: Ying-Tsai CHANG, Kuen-Yang TSAI, Ryan ZHANG, Meng-Chyi LIN
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Patent number: 9696377Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.Type: GrantFiled: July 29, 2015Date of Patent: July 4, 2017Assignee: SYNTEST TECHNOLOGIES, INC.Inventors: Laung-Terng Wang, Hsin-Po Wang, Xiaoqing Wen, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh, Sen-Wei Tsai, Khader S. Abdel-Hafez
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Patent number: 9449138Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.Type: GrantFiled: August 5, 2014Date of Patent: September 20, 2016Assignee: Synopsys, Inc.Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming-Yang Wang, Yu-Chin Hsu
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Patent number: 9384313Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.Type: GrantFiled: April 15, 2014Date of Patent: July 5, 2016Assignee: Synopsys, Inc.Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
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Publication number: 20150294055Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.Type: ApplicationFiled: April 15, 2014Publication date: October 15, 2015Applicants: Synopsys, Inc., Synopsys Taiwan Co., Ltd.Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
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Patent number: 9057763Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: GrantFiled: November 12, 2013Date of Patent: June 16, 2015Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Patent number: 9026875Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: GrantFiled: May 15, 2013Date of Patent: May 5, 2015Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Publication number: 20140351777Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file.Type: ApplicationFiled: August 5, 2014Publication date: November 27, 2014Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming-Yang Wang, Yu-Chin Hsu
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Patent number: 8839179Abstract: A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards.Type: GrantFiled: April 3, 2013Date of Patent: September 16, 2014Assignee: Synopsys Taiwan Co., Ltd.Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming Yang Wang, Yuchin Hsu
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Patent number: 8769359Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: GrantFiled: November 12, 2013Date of Patent: July 1, 2014Assignee: Syntest Technologies, Inc.Inventors: Luang-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Patent number: 8739089Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.Type: GrantFiled: August 28, 2012Date of Patent: May 27, 2014Assignees: Synopsys, Inc.Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
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Patent number: 8719762Abstract: A custom prototyping board and a controller are integrated to form an emulation system for emulating a circuit design. The controller may be disposed on an adaptor board. The custom prototyping board is defined by a set of board description files which further define the FPGA device(s) used in the system as well as the wire connections among the FPGA devices and connectors on the custom prototyping board. The FPGA device(s) is configured in accordance with the partitioned circuit design. Each partitioned circuit in the FPGA device is associated with a verification module for communicating with the controller to control and probe the emulation. A host workstation may be used to link with the controller to support co-simulation or co-emulation of the circuit design.Type: GrantFiled: December 28, 2012Date of Patent: May 6, 2014Assignee: Synopsys Taiwan Co., Ltd.Inventors: Yingtsai Chang, Sweyyan Shei, Meng-Chyi Lin, Hwa Mao, Ming Yang Wang, Yuchin Hsu
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Publication number: 20140082446Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: ApplicationFiled: November 12, 2013Publication date: March 20, 2014Applicant: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Publication number: 20140075256Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: ApplicationFiled: November 12, 2013Publication date: March 13, 2014Applicant: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Publication number: 20130268818Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: ApplicationFiled: May 15, 2013Publication date: October 10, 2013Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Publication number: 20130055177Abstract: User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.Type: ApplicationFiled: August 28, 2012Publication date: February 28, 2013Applicants: SPRINGSOFT USA, INC., SPRINGSOFT, INC.Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
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Patent number: 7970597Abstract: A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources.Type: GrantFiled: May 15, 2008Date of Patent: June 28, 2011Assignee: Springsoft, Inc.Inventors: Meng-Chyi Lin, Fei-Sheng Hsu, Sweyyan Shei
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Patent number: 7904773Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.Type: GrantFiled: October 1, 2008Date of Patent: March 8, 2011Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L. T.) Wang, Meng-Chyi Lin, Xiaoqing Wen, Hsin-Po Wang, Chi-Chan Hsu, Shih-Chia Kao, Fei-Sheng Hsu
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Patent number: 7779323Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: August 20, 2008Date of Patent: August 17, 2010Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaoqing Wen
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Patent number: 7721173Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.Type: GrantFiled: May 20, 2009Date of Patent: May 18, 2010Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Hsin-Po Wang, Xiaoqing Wen, Meng-Chyi Lin, Shyh-Horng Lin, Ta-Chia Yeh, Sen-Wei Tsai, Khader S. Abdel-Hafez