Patents by Inventor Meng Fan
Meng Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250252995Abstract: A method of operating a memory device is provided, including operations: generating, based on at least one weight stored in a first memory, a weight feature to be stored in a second memory different from the first memory, wherein the weight feature is associated with a number of repetitious bits, that are in neighbor positions of and the same as a most significant bit, in the at least one weight; and accessing, according to the weight feature and an address of the at least one weight, the first memory and the second memory to transmit the at least one weight to a multiply and accumulate circuit for a first neural network layer operation.Type: ApplicationFiled: February 7, 2024Publication date: August 7, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Win-San KHWA, De-Qi YOU, Jui-Jen WU, Meng-Fan CHANG
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Publication number: 20250251909Abstract: A circuit for data processing is provided. The circuit comprises a dual-mode adder, a max finder circuit, a zone detector circuit and an alignment circuit. The dual-mode adder generates products between first exponents of first floating point numbers and second exponents of second floating point numbers. The max finder circuit finds a maximum among first portions of the products. The zone detector circuit classify the first portions into zones by comparing the first portions and the maximum. The alignment circuit align first mantissas of the first floating point numbers according to the zones and second portions of the products to generate aligned mantissas for a floating point number operation.Type: ApplicationFiled: May 23, 2024Publication date: August 7, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Win-San KHWA, Ping-Chun WU, Jui-Jen WU, Meng-Fan CHANG
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Publication number: 20250253005Abstract: A memory device includes a memory array storing weights; a pre-charging circuit coupled to the memory array through data lines and charging, in response to a pre-charge signal, at least one data line in the data lines to a read voltage in a read operation to one in the weights; and a calibration circuit generating the pre-charge signal according to an address of the one in the weights.Type: ApplicationFiled: February 7, 2024Publication date: August 7, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Win-San KHWA, De-Qi YOU, Jui-Jen WU, Meng-Fan CHANG
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Publication number: 20250239285Abstract: In a matrix of SOT-MRAM cells, a first row is selected for writing and a second row is selected for reading. A first SOT-MRAM cell of the first row and a second SOT-MRAM of the second row are in a first column, while a third SOT-MRAM cell of the first row and a fourth SOT-MRAM of the second row are in a second column. The currents for writing the first SOT-MRAM cell and the third SOT-MRAM cell are in opposite direction. A first sense amplifier is configured to detect a voltage change on the first read bit line which is charged with a first read current in the second SOT-MRAM cell. A second sense amplifier is configured to detect a voltage change on the second read bit line which is discharged with a second read current in a fourth SOT-MRAM cell.Type: ApplicationFiled: June 4, 2024Publication date: July 24, 2025Inventors: Jui-Jen WU, Jen-Chieh LIU, Yi-Lun LU, Win-San KHWA, Meng-Fan CHANG
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Publication number: 20250239289Abstract: In this disclosure, a storage circuit is provided. The storage circuit includes a gain-cell, a self-refresh unit, and a latch circuit. The gain-cell is configured to store first data in a gate of a storage transistor. The self-refresh unit is configured to read the first data from the gain-cell and write the first data back to the gain-cell. The latch circuit is configured to read the first data from the self-refresh unit and latch the first data.Type: ApplicationFiled: January 22, 2024Publication date: July 24, 2025Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua UniversityInventors: Jui-Jen Wu, Ping-Chun Wu, Win-San Khwa, Meng-Fan Chang
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Publication number: 20250240976Abstract: An IC device includes first and second transistors and a memory device. The first transistor includes a first source/drain (S/D) terminal coupled to a first select line, a second S/D terminal, and a gate coupled to a first word line. The second transistor includes a first S/D terminal coupled to a first bit line, a second S/D terminal, and a gate. The memory device is coupled to the second S/D terminal of the second transistor, and a first storage node includes the second S/D terminal of the first transistor and the gate of the second transistor.Type: ApplicationFiled: June 4, 2024Publication date: July 24, 2025Inventors: Jui-Jen WU, Jen-Chieh LIU, Yi-Lun LU, Win-San KHWA, Meng-Fan CHANG
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Patent number: 12362027Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.Type: GrantFiled: April 15, 2024Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Win-San Khwa, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
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Patent number: 12362028Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.Type: GrantFiled: January 12, 2023Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
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Publication number: 20250224922Abstract: In some embodiments, a computing method includes, for a set of products, each of a respective pair of a first and a second floating-point operands, each having a respective mantissa and exponent, aligning the mantissas of the first operands based on a maximum exponent of the first operands to generate a shared exponent; modifying the mantissas of the first operands based on the shared exponent to generate respective adjusted mantissas of the first operands; generating mantissa products, each based on the mantissa of a respective one of the second operands and a respective one of the adjusted first mantissas retrieved from the memory device; summing the mantissas products to generate a mantissa product partial sum; and combining the shared exponent and the product mantissa partial sum. The adjusted mantissas of the first operands can be saved in, and retrieved from, a memory device for the mantissa product generation.Type: ApplicationFiled: April 24, 2024Publication date: July 10, 2025Inventors: Win-San KHWA, Hung-Hsi HSU, Xiaochen PENG, Murat Kerem Akarvardar, Meng-Fan Chang
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Patent number: 12354701Abstract: A circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third PMOS transistor coupled between the first data line and the first input terminal, a fourth PMOS transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node, and a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.Type: GrantFiled: March 25, 2024Date of Patent: July 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Jen Wu, Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang
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Patent number: 12356600Abstract: A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.Type: GrantFiled: March 24, 2022Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
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Publication number: 20250218474Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.Type: ApplicationFiled: March 21, 2025Publication date: July 3, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
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Publication number: 20250219620Abstract: A storage device includes an array of latching units and a plurality of inter-unit transmission switches. Each pair of two adjacent latching units is coupled together through an inter-unit transmission switch. Each latching unit includes a first inverter and a first transmission switch serially connected between a first bit node and a second bit node, and a second inverter and a second transmission switch serially connected between the second bit node and the first bit node. The first inverter has an input configured to receive a voltage from the first bit node either directly or through the first transmission switch. The second inverter has an input configured to receive a voltage from the second bit node either directly or through the second transmission switch.Type: ApplicationFiled: May 14, 2024Publication date: July 3, 2025Inventors: Ashwin Sanjay LELE, Win-San KHWA, Meng-Fan CHANG
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Patent number: 12347474Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.Type: GrantFiled: February 6, 2024Date of Patent: July 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang
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Patent number: 12334151Abstract: An integrated circuit includes a memory storage having bit cells, a write path switch configured to have a connection state determined by a reliability indicator, and a write driver having an input configured to receive an input data from a write terminal through either a first write path or a second write path. The input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. The reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.Type: GrantFiled: July 12, 2024Date of Patent: June 17, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Win-San Khwa, Jui Jen Wu, Jen-Chieh Liu, Meng-Fan Chang
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Publication number: 20250191628Abstract: In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.Type: ApplicationFiled: February 18, 2025Publication date: June 12, 2025Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
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Publication number: 20250166684Abstract: A sensing amplifier of a memory array, a memory device and a data read method with two state reference voltages are provided. The sensing amplifier comprises a sampling circuit, a latch circuit, and a reset circuit. The sampling circuit compares data voltages, a first state reference voltage, and a second state reference voltage according to a bit line pre-charge signal and a word line to generate a first sampling signal on the output node and a second sampling signal on the inverted output node. The latch circuit implements that the first sampling signal and the second sampling signal are inverted signals and latches the first sampling signal on an output node and the second sampling signal on the inverted output node.Type: ApplicationFiled: November 21, 2023Publication date: May 22, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Win-San Khwa, Meng-Fan Chang
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Publication number: 20250166699Abstract: A sensing method of a sense amplifier circuit is provided. The sense amplifier circuit comprises a differential amplifier. The differential amplifier comprises a first input node, a second input node, a first output node and a second output node. The sensing method comprising: providing a first switch and a second switch, wherein the first switch is coupled to the first input node and the first output node; pre-charging the first input node using a first output voltage of the first output node in response to a select signal by the first switch; and pre-charging the second input node using a second output voltage of the second output node in response to a select signal by the second switch.Type: ApplicationFiled: January 21, 2025Publication date: May 22, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
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Patent number: 12283340Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.Type: GrantFiled: August 11, 2022Date of Patent: April 22, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
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Publication number: 20250124980Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.Type: ApplicationFiled: December 23, 2024Publication date: April 17, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Meng-Fan CHANG, Yen-Cheng CHIU