Patents by Inventor Meng-Fan Chang

Meng-Fan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210247962
    Abstract: A memory unit with a multiply-accumulate assist scheme for a plurality of multi-bit convolutional neural network based computing-in-memory applications is controlled by a reference voltage, a word line and a multi-bit input voltage. The memory unit includes a non-volatile memory cell, a voltage divider and a voltage keeper. The non-volatile memory cell is controlled by the word line and stores a weight. The voltage divider includes a data line and generates a charge current on the data line according to the reference voltage, and a voltage level of the data line is generated by the non-volatile memory cell and the charge current. The voltage keeper generates an output current on an output node according to the multi-bit input voltage and the voltage level of the data line, and the output current is corresponding to the multi-bit input voltage multiplied by the weight.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Inventors: Meng-Fan CHANG, Han-Wen HU, Kuang-Tang CHANG
  • Publication number: 20210248478
    Abstract: A quantization method for a plurality of partial sums of a convolution neural network based on a computing-in-memory hardware includes a probability-based quantizing step and a margin-based quantizing step. The probability-based quantizing step includes a network training step, a quantization-level generating step, a partial-sum quantizing step, a first network retraining step and a first accuracy generating step. The margin-based quantizing step includes a quantization edge changing step, a second network retraining step and a second accuracy generating step. The quantization edge changing step includes changing a quantization edge of at least one of a plurality of quantization levels. The probability-based quantizing step is performed to generate a first accuracy value, and the margin-based quantizing step is performed to generate a second accuracy value. The second accuracy value is greater than the first accuracy value.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Inventors: Meng-Fan CHANG, Jing-Hong WANG, Ta-Wei LIU
  • Publication number: 20210216846
    Abstract: A transpose memory unit for a plurality of multi-bit convolutional neural network based computing-in-memory applications includes a memory cell and a transpose cell. The memory cell stores a weight. The transpose cell is connected to the memory cell and receives the weight from the memory cell. The transpose cell includes an input bit line, at least one first input word line, a first output bit line, at least one second input word line and a second output bit line. One of the at least one first input word line and the at least one second input word line transmits at least one multi-bit input value, and the transpose cell is controlled by the second word line to generate a multiply-accumulate output value on one of the first output bit line and the second output bit line according to the at least one multi-bit input value multiplied by the weight.
    Type: Application
    Filed: January 14, 2020
    Publication date: July 15, 2021
    Inventors: Meng-Fan CHANG, Jian-Wei SU, Yen-Chi CHOU, Ru-Hui LIU
  • Patent number: 11057224
    Abstract: A method for performing a physical unclonable function generated by a non-volatile memory write delay difference includes a resetting step, a writing step, a detecting step, a terminating step and a write-back operating step. The resetting step includes resetting two non-volatile memory cells controlled by a bit line and a bit line bar, respectively. The writing step includes performing a write operation on each of the two non-volatile memory cells. The detecting step includes detecting a voltage drop of each of the bit line and the bit line bar, and comparing the voltage drop and a predetermined voltage difference value to generate a comparison flag. The terminating step includes terminating the write operation on one of the two non-volatile memory cells according to the comparison flag. The write-back operating step includes performing a write-back operation on another of the two non-volatile memory cells.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: July 6, 2021
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventor: Meng-Fan Chang
  • Publication number: 20210203513
    Abstract: A method for performing a physical unclonable function generated by a non-volatile memory write delay difference includes a resetting step, a writing step, a detecting step, a terminating step and a write-back operating step. The resetting step includes resetting two non-volatile memory cells controlled by a bit line and a bit line bar, respectively. The writing step includes performing a write operation on each of the two non-volatile memory cells. The detecting step includes detecting a voltage drop of each of the bit line and the bit line bar, and comparing the voltage drop and a predetermined voltage difference value to generate a comparison flag. The terminating step includes terminating the write operation on one of the two non-volatile memory cells according to the comparison flag. The write-back operating step includes performing a write-back operation on another of the two non-volatile memory cells.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Inventor: Meng-Fan CHANG
  • Patent number: 11048650
    Abstract: A method for integrating a processing-in-sensor unit and an in-memory computing includes the following steps. A providing step is performed to transmit the first command signal and the initial data to the in-memory computing unit. A converting step is performed to drive the first command signal and the initial data to convert to a second command signal and a plurality of input data through a synchronizing module. A fetching step is performed to drive a frame difference module to receive the input data to fetch a plurality of difference data. A slicing step is performed to drive a bit-slicing module to receive the difference data and slice each of the difference data into a plurality of bit slices. A controlling step is performed to encode the difference address into a control signal, and the in-memory computing unit accesses each of the bit slices according to the control signal.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 29, 2021
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, Syuan-Hao Sie
  • Patent number: 11049550
    Abstract: A multi-bit current sense amplifier with pipeline current sampling of a resistive memory is configured to sense a plurality of bit line currents of a plurality of bit lines in a pipeline operation. A core sense circuit is connected to one part of the bit lines and generates a reference parallel resistance current and a reference anti-parallel resistance current. A plurality of bit line precharge branch circuits are connected to the core sense circuit and another part of the bit lines. The bit line currents of the bit lines, the reference parallel resistance current and the reference anti-parallel resistance current are sensed by the core sense circuit and the bit line precharge branch circuits in the pipeline operation so as to sequentially generate a plurality of voltage levels on the core sense circuit in a clock cycle.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 29, 2021
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tung-Cheng Chang, Chun-Ying Lee, Meng-Fan Chang
  • Publication number: 20210125663
    Abstract: A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a transpose cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The transpose cell is connected to the memory cell and receives the weight via the local bit line. The transpose cell includes an input bit line, an input bit line bar, an output bit line and an output bit line bar. Each of the input bit line and the input bit line bar transmits a multi-bit input value, and the transpose cell is controlled by the second word line to generate a multi-bit output value on each of the output bit line and the output bit line bar according to the multi-bit input value and the weight.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Meng-Fan CHANG, Yung-Ning TU, Xin SI, Wei-Hsing HUANG
  • Patent number: 10770142
    Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 8, 2020
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Wen-Zhang Lin, Li-Ya Lai
  • Patent number: 10748612
    Abstract: A sensing circuit with adaptive local reference generation of a resistive memory is configured to adaptively sense a first bit line current of a first bit line and a second bit line current of a second bit line via one sense amplifier. The sense amplifier has a first output node and a second output node. The adaptive local reference generator is electrically connected to the sense amplifier and generating a reference current equal to a sum of the second bit line current and a local reference current. A first bit line current flows through the first output node during a first bit line time interval. A second bit line current flows through the first output node during a second bit line time interval. The first bit line time interval is different from the second bit line time interval.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 18, 2020
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Wei-Yu Lin, Meng-Fan Chang
  • Patent number: 10734039
    Abstract: A voltage-enhanced-feedback sense amplifier of a resistive memory is configured to sense a first bit line and a second bit line. The voltage-enhanced-feedback sense amplifier includes a voltage sense amplifier and a voltage-enhanced-feedback pre-amplifier. The voltage-enhanced-feedback pre-amplifier is electrically connected to the voltage sense amplifier. A first bit-line amplifying module receives a voltage level of the second input node to suppress a voltage drop of the first bit line and amplifies a voltage level of the first input node according to a voltage level of the first bit line. A second bit-line amplifying module receives the voltage level of the first input node to suppress a voltage drop of the second bit line and amplifies the voltage level of the second input node according to a voltage level of the second bit line. A margin enhanced voltage difference is greater than a read voltage difference.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 4, 2020
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Huan-Ting Lin
  • Patent number: 10636481
    Abstract: A memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell includes a plurality of read-decoupled cells. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: April 28, 2020
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Xin Si, Yung-Ning Tu, Jia-Jing Chen
  • Publication number: 20200105315
    Abstract: A voltage-enhanced-feedback sense amplifier of a resistive memory is configured to sense a first bit line and a second bit line. The voltage-enhanced-feedback sense amplifier includes a voltage sense amplifier and a voltage-enhanced-feedback pre-amplifier. The voltage-enhanced-feedback pre-amplifier is electrically connected to the voltage sense amplifier. A first bit-line amplifying module receives a voltage level of the second input node to suppress a voltage drop of the first bit line and amplifies a voltage level of the first input node according to a voltage level of the first bit line. A second bit-line amplifying module receives the voltage level of the first input node to suppress a voltage drop of the second bit line and amplifies the voltage level of the second input node according to a voltage level of the second bit line. A margin enhanced voltage difference is greater than a read voltage difference.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Meng-Fan CHANG, Huan-Ting LIN
  • Patent number: 10607698
    Abstract: The present disclosure provides a control circuit of a memory array. The control circuit includes a first switch and a set termination circuit. The first switch is connected between a first voltage source and a data line of a resistive memory cell of the memory array. The set termination circuit has a first terminal connected to a control terminal of the first switch and a second terminal connected to the data line of the resistive memory cell of the memory array. When a data line voltage of the data line decreases to be lower than a first voltage in a first duration of the resistive memory cell performing a set operation, the set termination circuit turns off the first switch to terminate the set operation by stopping providing the first voltage of the first voltage source to the data line.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 31, 2020
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Wen-Zhang Lin, Li-Ya Lai
  • Patent number: 10510386
    Abstract: A dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal and includes a clamping node, a first clamping unit, a second clamping unit, a first feedback controlling unit and a second feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage and includes a switch. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node according to the at least one reference signal.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 17, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Wei-Hao Chen, Wei-Yu Lin
  • Patent number: 10510406
    Abstract: An operating method of the soft-verify write assist circuit of the resistive memory provides a voltage level applying step, a write operating step and a write voltage controlling step. The voltage level applying step is for applying a plurality of voltage levels to the reference voltage, the word line and the switching signal, respectively. The write operating step is for driving the memory cell to perform in a set process or a reset process via the first three-terminal switching element, the second three-terminal switching element and the soft-verify controlling unit during a write operation. The write voltage controlling step is for controlling the write voltage to be increased in the ramping cycle and decreased in the soft-verify cycle.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: December 17, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Huan-Ting Lin, Tsung-Yuan Huang, Wei-Hao Chen, Han-Wen Hu
  • Patent number: 10481965
    Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 19, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yih-Shan Yang, Shou-Nan Hung, Chun-Hsiung Hung, Yao-Jen Kuo, Meng-Fan Chang
  • Patent number: 10410690
    Abstract: A reference-free multi-level sensing circuit for computing-in-memory applications is controlled by a first bit line and a second bit line. An encoding unit generates a first register output value and a plurality of encoded values. The first register output value feedback controls a precharging unit so as to enable the precharging unit to precharge one of the first bit line and the second bit line according to the first register output value. A voltage level of the one of the first bit line and the second bit line is lower than a voltage level of the other one of the first bit line and the second bit line. The encoded values and the first register output value are formed a multi-bit signal to estimate voltage levels of the first bit line and the second bit line.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 10, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Jia-Jing Chen
  • Patent number: 10381071
    Abstract: A multi-bit computing circuit for computing-in-memory applications is controlled by an input port and includes a memory cell array and a capacitor sharing unit. The memory cell array includes a plurality of memory cells connected to the input port. The memory cells store a weight which is formed in two's complement. The capacitor sharing unit includes a plurality of switches, a plurality of capacitors and a sense amplifier. The switches are electrically connected to the memory cells, respectively. The capacitors are electrically connected to the switches, respectively. The sense amplifier is electrically connected to the capacitors and generates a total operational value. The capacitors are located among the switches and the sense amplifier, and the switches are switched to enable the total operational value to be equal to the input value multiplied by the weight. The present disclosure utilizes 8T SRAM cells without an extra DAC structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 13, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Xin Si, Meng-Fan Chang
  • Patent number: 10340003
    Abstract: An input-pattern aware reference generation system for a memory cell array having a plurality of word lines crossing a plurality of bit lines includes an input counting circuit, a reference array, and a reference word line control circuit. The input counting circuit receives the input signal of the memory cell array, discovers input activated word lines according to the input signal and generates a number signal representing a number of the input activated word lines. The reference array includes a plurality of reference memory cells storing a predetermined set of weights. The reference word line control circuit is electrically connected between the input counting circuit and the reference array. Moreover, the reference word line control circuit controls the reference array to generate a plurality of reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 2, 2019
    Assignee: National Tsing Hua University
    Inventors: Meng-Fan Chang, Wei-Hao Chen