Patents by Inventor Meng-Fan Chang

Meng-Fan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901004
    Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kerem Akarvardar, Win-San Khwa, Rawan Naous, Jin Cai, Meng-Fan Chang, Hon-Sum Philip Wong
  • Publication number: 20240021226
    Abstract: In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Publication number: 20230420041
    Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
  • Publication number: 20230420013
    Abstract: A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.
    Type: Application
    Filed: May 18, 2022
    Publication date: December 28, 2023
    Inventors: Win-San KHWA, Jui-Jen WU, Jen-Chieh LIU, Meng-Fan CHANG
  • Patent number: 11854594
    Abstract: A data processing method, a data processing circuit, and a computing apparatus are provided. In the method, data is obtained. A first value of a bit of the data is switched into a second value according to data distribution and an accessing property of memory. The second value of the bit is stored in the memory in response to switching the bit.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltpd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Publication number: 20230410926
    Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Publication number: 20230377645
    Abstract: A memory device includes a set of word lines, a set of bit lines, a source line having first and second source line contacts, a set of transistors serially coupled between the first and second source line contacts of the source line, and a set of data storage elements. The set of transistors has gates coupled to corresponding word lines in the set of word lines. Each data storage element in the set of data storage elements is coupled between a common terminal of a corresponding pair of adjacent transistors in the set of transistors, and a corresponding bit line in the set of bit lines.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Inventors: Jui-Jen WU, Win-San KHWA, Jen-Chieh LIU, Meng-Fan CHANG
  • Publication number: 20230360717
    Abstract: A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, Tung-Ying Lee, Jin Cai
  • Publication number: 20230326525
    Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kerem Akarvardar, Win-San Khwa, Rawan Naous, Jin Cai, Meng-Fan Chang, Hon-Sum Philip Wong
  • Publication number: 20230326518
    Abstract: A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jer-Fu Wang, Hung-Li Chiang, Yi-Tse Hung, Tzu-Chiang Chen, Meng-Fan Chang
  • Publication number: 20230317132
    Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.
    Type: Application
    Filed: May 23, 2022
    Publication date: October 5, 2023
    Inventors: Jen-Chieh Liu, Jui-Jen Wu, Win-San Khwa, Yi-Lun Lu, Meng-Fan Chang
  • Publication number: 20230317124
    Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.
    Type: Application
    Filed: August 21, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San KHWA, Ping-Chun WU, Tung Ying LEE, Meng-Fan CHANG
  • Patent number: 11778322
    Abstract: An electronic image stabilization (EIS) method includes: obtaining video frames derived from an output of an image sensor, wherein each of the video frames has a full field of view (FOV) of the image sensor; obtaining motion information of the video frames; dynamically estimating, by a processing circuit, EIS margins according to FOV variation of a plurality of cropped images within the video frames respectively; and applying stabilization correction to the cropped images according to the motion information and the EIS margins, to generate a plurality of stabilized images.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: October 3, 2023
    Assignee: MEDIATEK INC.
    Inventors: Hsiao-Wei Chen, Meng-Hung Cho, Yu-Chun Chen, Shu-Fan Wang, Te-Hao Chang, Ying-Jui Chen
  • Publication number: 20230309285
    Abstract: A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Publication number: 20230306245
    Abstract: A programming circuit includes a time difference converter circuit and a pulse generator circuit. The converter circuit is configured to receive a first pulse from a first neuron device and a second pulse from a second neuron device, and to output a time difference signal corresponding to a time difference between the first pulse and the second pulse. The pulse generator circuit includes an input coupled to the output of the time difference converter circuit to receive the time difference signal, and an output at which the pulse generator circuit is configured to output a program voltage corresponding to the time difference signal. The output of the pulse generator circuit is configured to be coupled to a synapse device coupled between the first neuron device and the second neuron device to program a weight value in the synapse device with the program voltage.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Inventors: Jen-Chieh LIU, Win-San KHWA, Jui-Jen WU, Meng-Fan CHANG
  • Publication number: 20230298651
    Abstract: A data processing method, a data processing circuit, and a computing apparatus are provided. In the method, data is obtained. A first value of a bit of the data is switched into a. second value according to data distribution and an accessing property of memory. The second value of the bit is stored in the memory in response to switching the bit.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Patent number: 11763162
    Abstract: A dynamic gradient calibration method for a computing-in-memory neural network is performed to update a plurality of weights in a computing-in-memory circuit according to a plurality of inputs corresponding to a correct answer. A forward operating step includes performing a bit wise multiply-accumulate operation on a plurality of divided inputs and a plurality of divided weights to generate a plurality of multiply-accumulate values, and performing a clamping function on the multiply-accumulate values to generate a plurality of clamped multiply-accumulate values according to a predetermined upper bound value, and comparing the clamped multiply-accumulate values with the correct answer to generate a plurality of loss values. A backward operating step includes performing a partial differential operation on the loss values relative to the weights to generate a weight-based gradient. The weights are updated according to the weight-based gradient.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: September 19, 2023
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Wei-Hsing Huang, Ta-Wei Liu
  • Publication number: 20230290402
    Abstract: A memory device that includes a memory array and a pre-charge selecting circuit is introduced. The memory array includes a plurality of memory cells that are coupled to a plurality of bit lines and a plurality of word lines, wherein the plurality of word lines are configured to receive an input vector. The pre-charge selecting circuit is configured to selectively pre-charge a selected bit line according to a value of the input vector. The pre-charge selecting circuit is configured to determine whether the value of the input vector is less than a predefined threshold, and generate a gated pre-charge signal to skip pre-charging the selected bit line in response to determining that the value of the input vector is less than the predefined threshold.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yen-Cheng Chiu, Je-Min Hung, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Patent number: 11756645
    Abstract: A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, Tung-Ying Lee, Jin Cai
  • Publication number: 20230282263
    Abstract: Memory circuits that read the bit state of memory cells are disclosed. In some embodiments, a memory circuit, includes a memory cell configured to store a bit. A reference line is configured to receive a reference signal and a data line is configured to receive a data signal. The data line is configured to be selectively coupled to the memory cell. A charge voltage select unit is configured to charge the reference line and the data line in response to a select signal being in a first select state and discharge the reference line and the data line in response to the select signal being in a second select state. A sense amplifier is configured to compare the data signal and the reference signal to sense a bit state of the bit stored by the memory cell.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 7, 2023
    Inventors: Yen-Cheng CHIU, Win-San KHWA, Meng-Fan CHANG