Abstract: A memory cell includes a write access transistor, a storage transistor, and a read access transistor. A gate of the write access transistor is connected to a write word line, a source of the write access transistor is connected to a write bit line, and a drain of the write access transistor is connected to a gate of the storage transistor. A source of the storage transistor is connected to a source line and a drain of the storage transistor is connected to a source of the read access transistor. A gate of the read access transistor is connected to a read bit line and a drain of the read access transistor is connected to read bit line. The memory cell further includes a capacitive element having a first connection to the gate of the storage transistor and a second connection to a reference voltage source.

Abstract: A resistive memory device includes a bottom electrode, a switching layer including a first horizontal portion, a second horizontal portion over an upper surface of the bottom electrode, and a first vertical portion over a side surface of the bottom electrode, a top electrode including a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer, and a conductive via contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode. By providing a switching layer and a top electrode which conform to a non-planar profile of the bottom electrode, charge crowding and a localized increase in electric field may facilitate resistance-state switching and provide a reduced operating voltage.

Abstract: The disclosure provides a memory device, a memory array, and an N-bit memory unit. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.

Abstract: An image processing device is provided. The device includes an electronic image stabilization (EIS) module and an image signal processing (ISP) module. The EIS module is configured to determine EIS information for a video frame based on motion information that corresponds to the video frame, wherein the EIS information is associated with the target region and the margin region of the video frame. The ISP module is configured to generate a processed video frame based on the EIS information by performing an ISP process only on the target region of the video frame and skipping the ISP process on the margin region of the video frame. The EIS module is further configured to generate a stabilized image based on the EIS information and the processed video frame.

Abstract: The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.

Abstract: A semiconductor device includes a memory cell including a first transistor, a second transistor, and a third transistor. The first transistor has a first gate terminal and the second transistor has a second gate terminal, the first gate terminal and the second gate terminal being connected to a first word line and a second word line, respectively. The first transistor has a pair of first source/drain terminals and the second transistor has a pair of second source/drain terminals, one of the pair of first source/drain terminals and one of the pair of second source/drain terminals being connected to a common bit line. The third transistor has a third gate terminal connected to the other of the pair of first source/drain terminals, and a pair of third source/drain terminals connected to the other of the pair of second source/drain terminals and a supply voltage, respectively.

Abstract: The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction.

Abstract: The present invention provides a differential varactor device including a substrate having a first conductive type, a well having a second conductive type, five doped regions having the second conductive type, a first gate, a second gate, a third gate, and a fourth gate. The well is disposed in the substrate, and the doped regions are disposed in the well and arranged along a direction. The first gate, the second gate, the third gate and the fourth gate are respectively disposed on the well between any two of the adjacent doped regions, and are arranged sequentially along the direction.