Abstract: A processing apparatus for overlay shift includes a storage unit and a control unit, and is applicable to a semiconductor wafer with several inspection regions. Each of the inspection regions has several sets of overlay marks for inspection. One set of overlay marks includes an original alignment mark without any overlay shift, and several split alignment marks with predetermined overlay shifts arranged near the original alignment mark. The original after-etch inspection (AEI) overlay data of the inspection regions is stored in the storage unit. The after-develop inspection (ADI) overlay data of the original alignment mark and the split alignment marks are compared with the original AEI overlay data by the control unit, thereby acquiring ADI pre-bias data of the original alignment mark and the split alignment marks. The control unit determines whether an overlay shift compensation is performed according to the acquired ADI pre-bias data.

Abstract: A handle assembly for an infant carrier is provided. The handle assembly allows the handle to be oriented in one of a plurality of positions, such as a stroller position, and infant carrier position and a car seat position. The handle assembly may include a locking mechanism allowing a handle extension to be extended only when the handle rotated to the stroller position. The handle assembly may also include a blocking mechanism that prevents the handle from rotating from the stroller position if the handle is extended.

Abstract: A display region includes a plurality of pixel driving circuitry setting regions arranged sequentially in a first direction, and each pixel driving circuitry setting region extends in a second direction intersecting the first direction. Each display circuitry includes a plurality of subpixels in one-to-one correspondence with the pixel driving circuitry setting regions, each subpixel includes a subpixel driving circuitry and a light-emitting element coupled to each other, the subpixel driving circuitry is located in a corresponding pixel driving circuitry setting region, the light-emitting element is located at a side of the subpixel driving circuitry away from the substrate, a width of the light-emitting element is greater than a width of the corresponding pixel driving circuitry setting region in the first direction, and a length of the light-emitting element is smaller than a length of the corresponding pixel driving circuitry setting region in the second direction.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes multiple chip regions and a strip line for separating the chip regions. A test key is formed in the strip line and is used for a bit line contact (BLC) resistance test. The test key includes active regions and connecting structures. The active regions are formed in the semiconductor substrate. The connecting structures are located at ends of the active regions. The multiple active regions located on the same column are sequentially connected end to end by the connecting structures.

Abstract: Examples of performing selective Fine Timing Measurement (FTM) are described. For an FTM scan cycle, a first AP (i.e., an initiator) may determine scanning parameter values of a plurality of second APs (i.e., potential responders) based on previously performed FTM scans. The first AP may determine weights of the plurality of second APs based on the scanning parameter values and select a set of target APs based on the weights. The first AP may then scan the set of target APs for the FTM scan so that the rest of the plurality of second APs are relieved from participating in the FTM scan thereby reducing the performance impact on the rest of the plurality of second APs. After the FTM scan cycle is completed, the first AP may update the weights and select another set of target APs based on the updated weights to perform another FTM scan cycle.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: Glasses with gesture recognition function include a glasses frame and a gesture recognition system. The gesture recognition system is disposed on the glasses frame and configured to detect hand gestures in front of the glasses thereby generating a control command. The gesture recognition system transmits the control command to an electronic device to correspondingly control the electronic device.

Abstract: A method for detecting an interior condition of a vehicle is provided to use a camera device and a radar device to acquire images and point cloud datasets with respect to an interior space of the vehicle. A computing device generates a synthesized image based on the images and the point cloud datasets, obtains a skeleton feature dataset and a facial feature dataset with respect to a living object in the synthesized image, and determines the interior condition of the vehicle based on the skeleton feature dataset and the facial feature dataset.

Abstract: An end cover assembly, an air cylinder, a tread sweeper and a railway vehicle.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.

Abstract: Provided by the present application are a Direct Current (DC) micro-grid system, a charging loop circuit and a control method thereof. The charging loop circuit selectively connects a charging loop to a first side loop or a second side loop through a set of switches.

Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

Abstract: The freshness of one or more terms in a documentation, indicative of a currency of the one or more terms is computed. Each term includes one or more constituent words, and the terms are visually marked as current or out-of-date based on the computed freshness. Upon marking a term as out-of-date, a latest term for the out-of-date term is retrieved or a most possible latest term for the out-of-date term is predicted.

Abstract: An information handling system includes a host processing system and a Liquid Crystal Display device. The host processing system includes a graphics processing unit (GPU) and the LCD device includes a memory device and a DisplayPort Configuration Data (DPCD) register. The host processing system 1) determines whether the first GPU supports a Dynamic Display Shifting (DDS) mode, 2) when the GPU does not support the DDS mode, provides a first indication to the LCD device that the GPU does not support the DDS mode, and 3) when the GPU supports the DDS mode, provides a second indication to the LCD device that the GPU supports the DDS mode. The LCD device retrieves a Panel Self Refresh (PSR) setting from the memory device and stores the PSR setting to the DPCD register in response to the first indication, and retrieves a DDS setting from the memory and stores the DDS setting to the DPCD register in response to the second indication.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A system may include a memory and a processor in communication with the memory. The processor may be configured to perform operations. The operations may include synchronizing a policy between a primary node and a compute node and maintaining a resource registry on a client of the primary node. The operations may include communicating a direct communication between the client and the compute node, and the direct communication may include a first task. The operations may include returning a first result for the first task directly from the compute node to the client.

Abstract: An electronic device is provided in this disclosure. The electronic device includes a display panel, a transmission line, a universal motherboard, and an optional panel power management module. The display panel is a first type display panel or a second type display panel. The transmission line is a first transmission line or a second transmission line. The universal motherboard is connected to the first type display panel through the first transmission line, or connected to the second type display panel through the second transmission line. When the display panel is the first type display panel, the panel power management module is connected to the universal motherboard and the first type display panel through the first transmission line, so that the panel power management module provides power management required for the first type display panel according to the universal motherboard.

Abstract: Various methods, apparatuses/systems, and media for implementing a security value generation module are disclosed. A processor establishes a communication link between a registry and a plurality of service devices each configured to provide corresponding service. A receiver receives a request from a user device for generating a value of a security based on a requested quality level. The processor implements rules to determine which service to be used for generating the value of the security based on the requested quality level in response to the received request; generates the value of the security based on the implemented rules; and transmits an electronic package to the user device, the package including data related to the value of the security.

Abstract: A liquid crystal display has position-adjustable light sources. The light sources may be lamps, LEDs, or other emissive components. The light sources, however, are movable to adjust the locations or positions of their light outputs. The light sources ride upon electromagnet carriers. When currents are applied to the electromagnet carriers, each electromagnet carrier creates a corresponding magnetic field. The magnetic fields cause neighboring electromagnet carriers to attract or to repel, depending on the magnitude/polarity of the currents. The lateral and vertical positions of the electromagnet carriers may thus be adjusted by varying their respective currents and magnetic fields. Because the light sources ride on the electromagnet carriers, the light sources may be moved to refine an image generated by the liquid crystal display. The light sources, for example, may be moved to improve white/black contracts to reduce halo-effects.