Abstract: The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.

Abstract: A waveguide probe structure, a calibration device for an antenna array and a calibration method for an antenna array are provided. The waveguide probe structure includes a waveguide coaxial converter, a tapered waveguide and a first straight waveguide. The waveguide coaxial converter is configured to transmit and receive two orthogonal linearly-polarized signals; the tapered waveguide includes a first waveguide cavity including a first waveguide port and a second waveguide port, the first waveguide port is connected to the waveguide coaxial converter, the second waveguide port is connected to the first straight waveguide, and a size of a cross section of the first waveguide cavity increases monotonically in a direction from the first waveguide port to the second waveguide port; the first straight waveguide includes a second waveguide cavity, a size of a cross section of the second waveguide cavity is equal to a size of the second waveguide port.

Abstract: A display device includes a display panel including a plurality of gate lines and a plurality of data lines, the plurality of gate lines intersecting and being insulated with the plurality of data lines, the display panel further including a plurality of sub-pixels arranged in an array, and the plurality of gate lines and the plurality of data lines defining areas where the sub-pixels are located; a gate driver electrically connected to the plurality of gate lines in the display panel; and a source driver bound to the display panel and electrically connected to the plurality of data lines in the display panel, the source driver being configured to set data transmission start time for respective data lines so that effective charging time of respective sub-pixels formed by the plurality of data lines and a same gate line is same.

Abstract: The present disclosure discloses a method, apparatus, device, and storage medium for training a model, relates to the technical fields of knowledge graph, natural language processing, and deep learning. The method may include: acquiring a first annotation data set, the first annotation data set including sample data and a annotation classification result corresponding to the sample data; training a preset initial classification model based on the first annotation data set to obtain an intermediate model; performing prediction on the sample data in the first annotation data set using the intermediate model to obtain a prediction classification result corresponding to the sample data; generating a second annotation data set based on the sample data, the corresponding annotation classification result, and the corresponding prediction classification result; and training the intermediate model based on the second annotation data set to obtain a classification model.

Abstract: An anti-glare apparatus includes a lens assembly having an incident side, the lens assembly including a layer of liquid crystal molecules, a first driving electrode and a second driving electrode respectively on both sides of the layer of the liquid crystal molecules, the first driving electrode or the second driving electrode including a plurality of sub-electrodes; a reflective layer on a side of the lens assembly opposite from the incident side; a camera, configured to acquire a human eye's position and acquire an intensity signal of incident light irradiating the incident side of the lens assembly; and a controller electrically connected to the first driving electrode, the second driving electrode, and the camera; where the controller is configured to adjust driving voltages of the sub-electrode based on the intensity signal of the incident light acquire by the camera to change the optical axis direction of the lens assembly.

Abstract: The compounds represented by Formula (I), which are peripheral alkyl and alkenyl chains extended benzene derivatives, are useful as dual autotaxin (ATX)/histone deacetylase (HD AC) inhibitors. These compounds may be included in a pharmaceutical composition along with a pharmaceutically acceptable carrier, and be used in a therapeutically effective amount for prophylaxis or treatment of various diseases and disorders.

Abstract: A phase calibration method for a phased array antenna is provided. The method includes: sequentially calibrating M×N antenna units based on a pre-obtained test voltage set including first test voltages; sequentially loading the first test voltages to the antenna unit in the ith row and the jth column, and acquiring phase and amplitude information of a microwave signal radiated by the antenna unit every time one first test voltage is loaded; acquiring first array vectors through analysis based on the phase and amplitude information of the acquired microwave signals of the antenna unit under different first test voltages; obtaining a calibration response vector of the antenna unit under each first test voltage in the test voltage set through a first preset algorithm based on the first array vector, and determining a target voltage-phase curve corresponding to the antenna unit in the ith row and the jth column.

Abstract: A pouch battery cell includes a pouch enclosure and a battery cell arranged in the pouch enclosure. A first terminal is connected to the battery cell through the pouch enclosure. A second terminal is connected to the battery cell through the pouch enclosure. A check valve includes a first gas channel in fluid communication with an inner volume of the pouch enclosure and a second gas channel. The check valve vents gas from the pouch enclosure when a difference between pressure at the first gas channel and the second gas channel is greater than a predetermined pressure difference and restricts flow of gas from the second gas channel to the first gas channel.

Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.

Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: The present disclosure provides an electronic device, which includes a substrate, a first data line arranged on the substrate and extending along a first direction, a first electrode and a second electrode arranged on the substrate and arranged along the first direction, and a third electrode and a fourth electrode arranged on the substrate and arranged along the first direction, the first electrode, the second electrode, the third electrode and the fourth electrode are electrically connected with the first data line, and the first electrode and the second electrode are located on a first side of the first data line, and the third electrode and the fourth electrode are located on a second side of the first data line relative to the first side.

Abstract: The present invention provides an image sensor module, including an integrated circuit substrate, an image sensing chip, a cover plate and an encapsulating material. The image sensing chip is disposed on the integrated circuit substrate. The image sensing chip includes an image sensing area and a non-image sensing area. A dam is disposed between the cover plate and the non-image sensing area of the image sensing chip. The cover plate includes a transparent material and a cushioning material. The encapsulating material covers the periphery of the image sensing chip, the periphery of the dam, part of the integrated circuit substrate and the periphery of the cover plate. The cushioning material is disposed between the transparent material and the dam and between the transparent material and the encapsulating material. The present invention reduces the possibility that the encapsulating material will peel off the cover plate.

Abstract: Disclosed is a method for manufacturing an image sensor module. The method comprises the steps of: disposing a glass cover on a substrate; sawing the glass cover into a plurality of glass units; forming an individual solidified interface filler between the adjacent glass units; sawing along the centerline of each solidified interface filler to form a plurality of independent electronic semi-finished products for complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS) packaging; and performing an image sensor molded ball grid array (ImBGA) process to obtain the image sensor module.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: The invention relates to a coated film and a method for preparing the same, use of the coated film for manufacturing shaped bodies, a method for manufacturing shaped bodies from the coated film, and a shaped body made therefrom. The coated film comprises a plastic film with Shore hardness of not less than 80A and a coating formed by applying an aqueous coating composition to the plastic film, wherein the plastic film is a film of a thermoplastic polyurethane based on polyester polyol, and the aqueous coating composition comprises: a. 45% by weight to 85% by weight of a dispersion of an anionic polyurethane based on polycarbonate polyol; b. 0% by weight to 40% by weight of a dispersion of an anionic polyurethane based on polyether polyol; c. 2% by weight to 18% by weight of a dispersion of anionic silica; d. 0.5% by weight to 10% by weight of a blocked isocyanate; and e. 0.1% by weight to 10% by weight of an additive; the amounts above being relative to the total weight of the composition.

Abstract: According to one embodiment, a method, computer system, and computer program product for adjusting an audible area of an avatar's voice is provided. The present invention may include receiving, at a microphone, a source audio; creating a received audio; calculating, by a generative model, a voice propagation distance of a user based on the source audio, the received audio, and a templated text sentence describing a category of a mixed reality environment experienced by the user; drawing a virtual circle within the mixed reality environment centered on a user avatar representing the user and with a radius equal to the voice propagation distance; and transmitting the source audio to one or more participants within the mixed-reality environment represented by one or more participant avatars located within the virtual circle.

Abstract: The present application provides an unmanned aerial vehicle (UAV) for a long duration flight. An exemplary UAV may include a UAV body assembly. The UAV may also include a flight control system (FCS) coupled to the UAV body assembly. The UAV may further include a motor coupled to the UAV body assembly at one end and coupled to a propeller at the other end. The FCS is communicatively connected to the motor. A center of gravity (CG) of the UAV is at a point between 21% and 25% of a mean aerodynamic chord (MAC) of the UAV.

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.