Patents by Inventor Meng-Feng Tsai
Meng-Feng Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147711Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
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Publication number: 20240134291Abstract: A processing apparatus for overlay shift includes a storage unit and a control unit, and is applicable to a semiconductor wafer with several inspection regions. Each of the inspection regions has several sets of overlay marks for inspection. One set of overlay marks includes an original alignment mark without any overlay shift, and several split alignment marks with predetermined overlay shifts arranged near the original alignment mark. The original after-etch inspection (AEI) overlay data of the inspection regions is stored in the storage unit. The after-develop inspection (ADI) overlay data of the original alignment mark and the split alignment marks are compared with the original AEI overlay data by the control unit, thereby acquiring ADI pre-bias data of the original alignment mark and the split alignment marks. The control unit determines whether an overlay shift compensation is performed according to the acquired ADI pre-bias data.Type: ApplicationFiled: October 12, 2023Publication date: April 25, 2024Inventors: Meng-Hsien TSAI, Cheng-Shuai LI, Yueh-Feng LU, Kao-Tsair TSAI
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Patent number: 11961774Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes multiple chip regions and a strip line for separating the chip regions. A test key is formed in the strip line and is used for a bit line contact (BLC) resistance test. The test key includes active regions and connecting structures. The active regions are formed in the semiconductor substrate. The connecting structures are located at ends of the active regions. The multiple active regions located on the same column are sequentially connected end to end by the connecting structures.Type: GrantFiled: September 3, 2021Date of Patent: April 16, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Chen Huang, Meng-Feng Tsai
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Patent number: 11955460Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.Type: GrantFiled: October 5, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20230021007Abstract: A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: YI JIANG, Deyuan XIAO, Qinghua HAN, MENG-FENG TSAI
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Publication number: 20220077009Abstract: A semiconductor structure is provided with a test region. In test region, the semiconductor structure includes a semiconductor substrate, a plurality of bit line contact structures arranged on semiconductor substrate and a plurality of wire groups. The semiconductor structure is provided with a plurality of separate active regions extending along a first direction. In first direction, each active region is electrically connected to two bit line contact structures. The plurality of wire groups are arranged along a second direction. Each wire group includes a plurality of wires extending along a third direction. In third direction, each of two bit line contact structures for each active region is connected to respective one of two bit line contact structures for active region adjacent to said each active region by a respective one of wires, so that two wire groups of the wire groups cooperate with each other to form a conductive path.Type: ApplicationFiled: September 20, 2021Publication date: March 10, 2022Inventors: Chen HUANG, MENG-FENG TSAI, Yuejiao SHU
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Publication number: 20220077008Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes multiple chip regions and a strip line for separating the chip regions. A test key is formed in the strip line and is used for a bit line contact (BLC) resistance test. The test key includes active regions and connecting structures. The active regions are formed in the semiconductor substrate. The connecting structures are located at ends of the active regions. The multiple active regions located on the same column are sequentially connected end to end by the connecting structures.Type: ApplicationFiled: September 3, 2021Publication date: March 10, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Chen HUANG, MENG-FENG TSAI
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Patent number: 9202203Abstract: A method for classifying email includes receiving an email. Several recipient email accounts of the email are extracted. Several email feature values of the email are generated according to the recipient email accounts. A classification algorithm is utilized to classify the email as an official email or a private email according to the email feature values of the email.Type: GrantFiled: July 6, 2012Date of Patent: December 1, 2015Assignee: National Central UniversityInventors: Meng-Feng Tsai, Min-Feng Wang, Hsiao-Kuang Wu, Sie-Long Jheng, Hsin-Fu Su, Cheng-Hsien Tang, Chi-Sheng Huang
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Patent number: 8843521Abstract: A method for analyzing data utilizing a weighted suffix tree includes receiving at least one original data sequence. An original data sequence ID is assigned to the original data sequence, and the original data sequence includes an original datums. A weighted suffix tree is constructed according to the original datums of the original data sequence. The weighted suffix tree includes several nodes, and each node includes a weight set which is formed by the original data sequence ID. Group information for classifying the original datums into several groups is received. The nodes of the weighted suffix tree belonging to a same group are merged according to the group information. Data is analyzed according to the weighted suffix tree after being merged.Type: GrantFiled: July 6, 2012Date of Patent: September 23, 2014Assignee: National Central UniversityInventors: Meng-Feng Tsai, Min-Feng Wang, Cheng-Hsien Tang, Bo-Ru Song, Ching-Hsuan Shen, Hsin-Fu Su, Chi-Sheng Huang
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Patent number: 8709946Abstract: A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer.Type: GrantFiled: February 1, 2012Date of Patent: April 29, 2014Assignee: Powerchip Technology CorporationInventors: Meng-Feng Tsai, Yi-Shiang Chang, Chia-Chi Lin, I-Hsin Chen, Chia-Ming Wu
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Publication number: 20140076487Abstract: A method of forming a flexible implement grip utilizing a cured underlist. A sleeve is formed of uncured sheet stock laminated with a carrier having a design thereon of heat transferable colored ink. The laminate is cut to a pattern, wrapped on a core bar and heated in a mold with textured/embossed cavities. The design is heat transferred to the sheet stock in the molding and upon removal from the mold, the carrier and core bar are removed to leave a seamless tubular sleeve with the colored design on the outer surface. The sleeve is then assembled on the underlist and adhesively secured thereon forming a finished grip.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: Eaton CorporationInventors: Wen-Chen Su, Alex Lee Walls, Min-Chia Wang, Meng-Feng Tsai
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Publication number: 20130248089Abstract: In one version of the method of making a flexible grip, a thin film carrier with negative of desired colored image is laminated to an uncured skin sheet and flat cured in a mold to heat transfer the image to the skin sheet and concurrently form a textured surface. The carrier is peeled away and the skin sheet wrapped and adhesively bonded to a cured underlist. In another version, the thin film carrier with negative of desired image is laminated on an uncured skin sheet which is wrapped on a cured underlist. The wrapped underlist is cured in a textured mold cavity to concurrently, in a single molding operation, heat transfer the image of the skin sheet from a textured surface and cure the skin sheet in place on the underlist.Type: ApplicationFiled: March 21, 2012Publication date: September 26, 2013Inventors: Wen-Chen Su, Alex Lee Walls, Min-Chia Wang, Meng-Feng Tsai
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Publication number: 20130179516Abstract: A method for classifying email includes receiving an email. Several recipient email accounts of the email are extracted. Several email feature values of the email are generated according to the recipient email accounts. A classification algorithm is utilized to classify the email as an official email or a private email according to the email feature values of the email.Type: ApplicationFiled: July 6, 2012Publication date: July 11, 2013Applicant: NATIONAL CENTRAL UNIVERSITYInventors: Meng-Feng TSAI, Min-Feng WANG, Hsiao-Kuang WU, Sie-Long JHENG, Hsin-Fu SU, Cheng-Hsien TANG, Chi-Sheng HUANG
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Publication number: 20130179393Abstract: A method for analyzing data utilizing a weighted suffix tree includes receiving at least one original data sequence. An original data sequence ID is assigned to the original data sequence, and the original data sequence includes an original datums. A weighted suffix tree is constructed according to the original datums of the original data sequence. The weighted suffix tree includes several nodes, and each node includes a weight set which is formed by the original data sequence ID. Group information for classifying the original datums into several groups is received. The nodes of the weighted suffix tree belonging to a same group are merged according to the group information. Data is analyzed according to the weighted suffix tree after being merged.Type: ApplicationFiled: July 6, 2012Publication date: July 11, 2013Applicant: NATIONAL CENTRAL UNIVERSITYInventors: Meng-Feng TSAI, Min-Feng WANG, Cheng-Hsien TANG, Bo-Ru SONG, Ching-Hsuan SHEN, Hsin-Fu SU, Chi-Sheng HUANG
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Publication number: 20130137270Abstract: A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer.Type: ApplicationFiled: February 1, 2012Publication date: May 30, 2013Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Meng-Feng Tsai, Yi-Shiang Chang, Chia-Chi Lin, I-Hsin Chen, Chia-Ming Wu
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Patent number: 8105897Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: GrantFiled: December 24, 2009Date of Patent: January 31, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Tsai, Jiang Guang Chang
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Patent number: 8105899Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region.Type: GrantFiled: December 24, 2009Date of Patent: January 31, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Tsai, Jian Guang Chang
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Patent number: 8105898Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: GrantFiled: December 24, 2009Date of Patent: January 31, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Tsai, Jian Guang Chang
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Patent number: 8097508Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.Type: GrantFiled: December 24, 2009Date of Patent: January 17, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Lily Jiang, Meng Feng Tsai, Jian Guang Chang
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Patent number: 8095235Abstract: A method for control of humidity and auto-dispensing of pills in a pill box includes a box having multiple rooms defined therein which are shifted to be in alignment with an outlet. The method controls the humidity in each of the rooms and provides a control unit which controls a transmission unit to proceed a mechanical action to shift the rooms to be in alignment with the outlet according to a time setting signal so as to dispense at least one pill. The method includes a display unit to display time information and provides a reminder to take pills by way of audio and/or light.Type: GrantFiled: December 23, 2009Date of Patent: January 10, 2012Assignee: Southern Taiwan UniversityInventors: Hsinn-Jyh Tzeng, Ting-Wei Yang, Tsan-Cheng Yang, Chih-Chun Chang, Meng-Feng Tsai, Chih-Tung Su